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| regarding the change of names mentioned in the document, such as hitachi electric and hitachi xx, to renesas technology corp. the semiconductor operations of mitsubishi electric and hitachi were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although hitachi, hitachi, ltd., hitachi semiconductors, and other hitachi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. renesas technology home page: http://www.renesas.com renesas technology corp. customer support dept. april 1, 2003 to all our customers
cautions keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or an y other rights, belonging to renesas technology corporation or a third party. 2. renesas technology corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained i n these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas technology corporation semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, an d algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lice nse from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein. h8/3714 series hd6433712 hd6433713 hd6433714, HD6473714 hardware manual preface the h8/300l series of single-chip microcomputers has the high-speed h8/300l cpu at its core, with many necessary peripheral functions on-chip. the h8/300l cpu instruction set is compatible with the h8/300 cpu, and is ideal for realtime control. the h8/3714 series has a system-on-a-chip architecture that includes such peripheral functions as a vacuum fluorescent display controller/driver, five timers, a 14-bit pwm, a two-channel serial communication interface, and an a/d converter. it also has high-voltage pins capable of directly driving a vacuum fluorescent display, making it ideal for use in systems employing this type of display. this manual describes the hardware of the h8/3714 series. for details on the instruction set, refer to the h8/300l series programming manual. contents section 1 overview .......................................................................................................... 1 1.1 overview.................................................................................................................... ..... 1 1.2 internal block diagram .................................................................................................. 5 1.3 pin arrangement and functions ..................................................................................... 6 1.3.1 pin arrangement................................................................................................. 6 1.3.2 pin functions ...................................................................................................... 8 section 2 cpu ................................................................................................................... 15 2.1 overview.................................................................................................................... ..... 15 2.1.1 features............................................................................................................... 15 2.1.2 address space..................................................................................................... 16 2.1.3 register configuration........................................................................................ 17 2.2 register descriptions...................................................................................................... 1 8 2.2.1 general registers................................................................................................ 18 2.2.2 control registers ................................................................................................ 18 2.2.3 initial register values......................................................................................... 20 2.3 data formats................................................................................................................ ... 20 2.3.1 data formats in general registers ..................................................................... 21 2.3.2 memory data formats ........................................................................................ 22 2.4 addressing modes .......................................................................................................... 23 2.4.1 addressing modes .............................................................................................. 23 2.4.2 effective address calculation ............................................................................ 25 2.5 instruction set............................................................................................................. .... 29 2.5.1 data transfer instructions .................................................................................. 31 2.5.2 arithmetic operations ........................................................................................ 33 2.5.3 logic operations ................................................................................................ 34 2.5.4 shift operations .................................................................................................. 34 2.5.5 bit manipulations ............................................................................................... 36 2.5.6 branching instructions........................................................................................ 40 2.5.7 system control instructions ............................................................................... 42 2.5.8 block data transfer instruction ......................................................................... 43 2.6 cpu states .................................................................................................................. .... 45 2.6.1 overview............................................................................................................. 45 2.6.2 program execution state .................................................................................... 46 2.6.3 program halt state.............................................................................................. 46 2.6.4 exception-handling state................................................................................... 46 2.7 basic operation timing.................................................................................................. 47 2.7.1 access to on-chip memory (ram, rom) ....................................................... 47 2.7.2 access to on-chip peripheral modules ............................................................. 48 2.8 application notes ........................................................................................................... 49 2.8.1 notes on data access ......................................................................................... 49 2.8.2 notes on bit manipulation.................................................................................. 51 section 3 system control .............................................................................................. 55 3.1 overview.................................................................................................................... ..... 55 3.2 exception handling ........................................................................................................ 55 3.2.1 reset ................................................................................................................... 55 3.2.2 interrupts............................................................................................................. 56 3.2.3 interrupt control registers ................................................................................. 58 3.2.4 external interrupts .............................................................................................. 66 3.2.5 internal interrupts ............................................................................................... 67 3.2.6 interrupt operations............................................................................................ 67 3.2.7 return from an interrupt..................................................................................... 72 3.2.8 interrupt response time..................................................................................... 72 3.2.9 valid interrupts in each mode............................................................................ 73 3.2.10 notes on stack area use .................................................................................... 74 3.3 system modes................................................................................................................ .75 3.3.1 active mode ....................................................................................................... 76 3.3.2 low-power operation mode .............................................................................. 76 3.3.3 application notes ............................................................................................... 82 3.4 system control registers ............................................................................................... 83 3.4.1 system control register 1 (syscr1)................................................................ 83 3.4.2 system control register 2 (syscr2)................................................................ 85 section 4 rom .................................................................................................................. 87 4.1 overview.................................................................................................................... ..... 87 4.1.1 block diagram.................................................................................................... 87 4.2 prom mode................................................................................................................... 88 4.2.1 selection to prom mode................................................................................... 88 4.2.2 socket adapter pin arrangement and memory map ......................................... 88 4.3 programming ................................................................................................................. .91 4.3.1 writing and verifying ......................................................................................... 91 4.3.2 programming precautions................................................................................... 94 4.3.3 reliability of written data ................................................................................. 96 section 5 ram ................................................................................................................. 97 5.1 overview.................................................................................................................... ..... 97 5.1.1 block diagram.................................................................................................... 97 5.1.2 display ram area ............................................................................................. 97 section 6 clock pulse generators ............................................................................... 99 6.1 overview.................................................................................................................... ..... 99 6.1.1 block diagram.................................................................................................... 99 6.2 system clock generator ................................................................................................. 100 6.3 subclock generator ........................................................................................................ 10 3 section 7 i/o ports ........................................................................................................... 105 7.1 overview.................................................................................................................... ..... 105 7.1.1 port types and mask options............................................................................. 107 7.1.2 mos pull-up ...................................................................................................... 108 7.1.3 mos pull-down ................................................................................................. 110 7.2 port 0 ...................................................................................................................... ...... 111 7.2.1 overview............................................................................................................. 111 7.2.2 register configuration and description ............................................................. 111 7.2.3 pin functions ...................................................................................................... 112 7.2.4 pin states ............................................................................................................ 112 7.3 port 1 ...................................................................................................................... ...... 113 7.3.1 overview............................................................................................................. 113 7.3.2 register configuration and description ............................................................. 113 7.3.3 pin functions ...................................................................................................... 118 7.3.4 pin states ............................................................................................................ 119 7.4 port 4 ...................................................................................................................... ...... 120 7.4.1 overview............................................................................................................. 120 7.4.2 register configuration and description ............................................................. 120 7.4.3 pin functions ...................................................................................................... 121 7.4.4 pin states ............................................................................................................ 121 7.5 port 5 ...................................................................................................................... ...... 122 7.5.1 overview............................................................................................................. 122 7.5.2 register configuration and description ............................................................. 122 7.5.3 pin functions ...................................................................................................... 123 7.5.4 pin states ............................................................................................................ 123 7.6 port 6 ...................................................................................................................... ...... 124 7.6.1 overview............................................................................................................. 124 7.6.2 register configuration and description ............................................................. 124 7.6.3 pin functions ...................................................................................................... 125 7.6.4 pin states ............................................................................................................ 125 7.7 port 7 ...................................................................................................................... ...... 126 7.7.1 overview............................................................................................................. 126 7.7.2 register configuration and description ............................................................. 126 7.7.3 pin functions ...................................................................................................... 127 7.7.4 pin states ............................................................................................................ 127 7.8 port 9 ...................................................................................................................... ...... 128 7.8.1 overview............................................................................................................. 128 7.8.2 register configuration and description ............................................................. 128 7.8.3 pin functions ...................................................................................................... 132 7.8.4 pin states ............................................................................................................ 134 section 8 timers ............................................................................................................... 135 8.1 overview.................................................................................................................... ..... 135 8.1.1 prescaler operation............................................................................................. 136 8.2 timer a..................................................................................................................... ...... 138 8.2.1 overview............................................................................................................. 138 8.2.2 register descriptions.......................................................................................... 139 8.2.3 timer operation.................................................................................................. 141 8.3 timer b ..................................................................................................................... ...... 143 8.3.1 overview............................................................................................................. 143 8.3.2 register descriptions.......................................................................................... 144 8.3.3 timer operation.................................................................................................. 146 8.4 timer c ..................................................................................................................... ...... 148 8.4.1 overview............................................................................................................. 148 8.4.2 register descriptions.......................................................................................... 149 8.4.3 timer operation.................................................................................................. 152 8.5 timer d..................................................................................................................... ...... 154 8.5.1 overview............................................................................................................. 154 8.5.2 register descriptions.......................................................................................... 155 8.5.3 timer operation.................................................................................................. 157 8.6 timer e ..................................................................................................................... ...... 158 8.6.1 overview............................................................................................................. 158 8.6.2 register descriptions.......................................................................................... 160 8.6.3 timer operation.................................................................................................. 164 8.7 interrupts.................................................................................................................. ....... 167 8.8 application notes ........................................................................................................... 167 section 9 14-bit pwm ................................................................................................... 169 9.1 overview.................................................................................................................... ..... 169 9.1.1 features............................................................................................................... 169 9.1.2 block diagram.................................................................................................... 169 9.1.3 pin configuration................................................................................................ 170 9.1.4 register configuration........................................................................................ 170 9.2 register descriptions...................................................................................................... 1 71 9.2.1 pwm control register (pwcr) ........................................................................ 171 9.2.2 pwm data registers u and l (pwdru, pwdrl) .......................................... 172 9.3 operation ................................................................................................................... ..... 173 section 10 sci1 .................................................................................................................. 175 10.1 overview................................................................................................................... ...... 175 10.1.1 features............................................................................................................... 17 5 10.1.2 block diagram.................................................................................................... 175 10.1.3 pin configuration................................................................................................ 176 10.1.4 register configuration........................................................................................ 176 10.2 register descriptions...................................................................................................... 177 10.2.1 serial mode register 1 (smr1) ......................................................................... 177 10.2.2 serial data register u1 (sdru1) ...................................................................... 178 10.2.3 serial data register l1 (sdrl1)....................................................................... 179 10.2.4 serial port register 1 (spr1) ............................................................................. 179 10.2.5 port mode register 2 (pmr2) ............................................................................ 180 10.2.6 port mode register 3 (pmr3) ............................................................................ 181 10.3 operation .................................................................................................................. ...... 182 10.3.1 overview............................................................................................................. 182 10.3.2 data transfer format.......................................................................................... 183 10.3.3 clock................................................................................................................... 1 83 10.3.4 data transmit/receive........................................................................................ 183 10.3.5 sci1 state transitions ........................................................................................ 186 10.3.6 serial clock error detection .............................................................................. 187 10.3.7 interrupts............................................................................................................. 18 8 section 11 sci2 .................................................................................................................. 189 11.1 overview................................................................................................................... ...... 189 11.1.1 features............................................................................................................... 18 9 11.1.2 block diagram.................................................................................................... 189 11.1.3 pin configuration................................................................................................ 190 11.1.4 register configuration........................................................................................ 190 11.2 register descriptions...................................................................................................... 191 11.2.1 start address register (star)........................................................................... 191 11.2.2 end address register (edar) ........................................................................... 191 11.2.3 serial control register 2 (scr2) ....................................................................... 192 11.2.4 status register (stsr) ....................................................................................... 193 11.2.5 port mode register 3 (pmr3) ............................................................................ 195 11.3 operation .................................................................................................................. ...... 197 11.3.1 overview............................................................................................................. 197 11.3.2 clock................................................................................................................... 1 98 11.3.3 data transfer format.......................................................................................... 198 11.3.4 data transmit/receive........................................................................................ 200 11.4 interrupts................................................................................................................. ........ 202 11.5 application notes .......................................................................................................... . 202 section 12 vfd controller/driver ................................................................................ 203 12.1 overview................................................................................................................... ...... 203 12.1.1 features............................................................................................................... 20 3 12.1.2 block diagram.................................................................................................... 203 12.1.3 pin configuration................................................................................................ 204 12.1.4 register configuration........................................................................................ 204 12.2 register descriptions...................................................................................................... 205 12.2.1 vfd digit control register (vfdr) ................................................................. 205 12.2.2 vfd segment control register (vfsr) ............................................................ 208 12.2.3 digit beginning register (dbr) ........................................................................ 210 12.3 operation .................................................................................................................. ...... 212 12.3.1 overview............................................................................................................. 212 12.3.2 control section ................................................................................................... 212 12.3.3 ram bit correspondence to digits/segments................................................... 212 12.3.4 procedure for starting operation........................................................................ 214 12.4 interrupts................................................................................................................. ........ 214 12.5 occurrence of flicker when vfd registers are rewritten ............................................ 214 section 13 a/d converter ................................................................................................ 215 13.1 overview................................................................................................................... ...... 215 13.1.1 features............................................................................................................... 21 5 13.1.2 block diagram.................................................................................................... 216 13.1.3 pin configuration................................................................................................ 217 13.1.4 register configuration........................................................................................ 217 13.2 register descriptions...................................................................................................... 218 13.2.1 a/d result register (adrr) ............................................................................. 218 13.2.2 a/d mode register (amr) ................................................................................ 218 13.2.3 a/d start register (adsr) ................................................................................ 221 13.2.4 port mode register 0 (pmr0) ............................................................................ 222 13.3 operation .................................................................................................................. ...... 222 13.4 interrupts................................................................................................................. ........ 222 13.5 typical use ................................................................................................................ ..... 223 13.6 application notes .......................................................................................................... . 227 section 14 electrical specifications .............................................................................. 229 14.1 absolute maximum ratings ........................................................................................... 229 14.2 HD6473714 electrical characteristics ........................................................................... 230 14.2.1 HD6473714 dc characteristics ......................................................................... 230 14.2.2 HD6473714 ac characteristics ......................................................................... 236 14.2.3 HD6473714 a/d converter characteristics ....................................................... 239 14.3 hd6433712, hd6433713 and hd6433714 electrical characteristics .......................... 240 14.3.1 hd6433712, hd6433713 and hd6433714 dc characteristics........................ 240 14.3.2 hd6433712, hd6433713 and hd6433714 ac characteristics ........................ 246 14.3.3 hd6433712, hd6433713 and hd6433714 a/d converter characteristics...... 249 14.4 operational timing......................................................................................................... 250 14.5 differences in electrical characteristics between HD6473714 and hd6433712/hd6433713/hd6433714........................................................................... 253 appendix a cpu instruction set ................................................................................... 255 a.1 instruction notation ........................................................................................................ 255 a.2 operation code map....................................................................................................... 256 a.3 number of states required for execution...................................................................... 258 appendix b on-chip registers ...................................................................................... 265 b.1 on-chip registers (1)..................................................................................................... 26 5 b.2 on-chip registers (2)..................................................................................................... 26 8 appendix c i/o port block diagrams ......................................................................... 295 c.1 port 0 block diagram ..................................................................................................... 295 c.2 port 1 block diagram ..................................................................................................... 296 c.3 port 4 block diagram ..................................................................................................... 299 c.4 port 5 block diagram ..................................................................................................... 300 c.5 port 6 block diagram ..................................................................................................... 301 c.6 port 7 block diagram ..................................................................................................... 302 c.7 port 9 block diagram ..................................................................................................... 303 appendix d port states in each processing state .................................................... 309 appendix e list of mask options ................................................................................. 311 appendix f rise time and fall time of high-voltage pins ................................. 312 appendix g package dimensions ................................................................................. 313 section 1 overview 1.1 overview the h8/300l series is a series of single-chip microcontrollers (mcu: microcomputer unit) built around the high-speed h8/300l cpu and equipped with peripheral system functions on-chip. within the h8/300l series, the h8/3714 series microcontrollers are equipped with high-voltage pins. on-chip peripheral functions include a vacuum fluorescent display (vfd) controller/driver, timers, a 14-bit pulse width modulator (digital-to-analog converter), two serial communication interface channels, and an analog-to-digital converter. together, these functions make the h8/3714 series ideally suited for embedded control of systems requiring a vacuum fluorescent display. on-chip memory is 16 kbytes of rom and 384 bytes of ram in the h8/3712, 24 kbytes of rom and 384 bytes of ram in the h8/3713, or 32 kbytes of rom and 512 bytes of ram in the h8/3714, providing a choice for systems of different sizes. the ztat * versions of the h8/3714 come with user-programmable prom. table 1 summarizes the features of the h8/3714 series. note: * ztat (zero turn-around time) is a trademark of hitachi, ltd. 1 table 1-1 features item description cpu general-register architecture general registers: sixteen 8-bit registers (can be used as eight 16-bit registers) operating speed max. operating speed: 4.19 mhz add/subtract: 0.5 ? (operating at f = 4 mhz) multiply/divide: 3.5 ? (operating at f = 4 mhz) can run on 32 khz subclock instruction set compatible with h8/300 cpu instruction length of 2 bytes or 4 bytes basic arithmetic operations between registers mov instruction for data transfer between memory and registers instruction features multiply (8 bits 8 bits) divide (16 bits ? 8 bits) bit accumulator register-indirect designation of bit position memory h8/3714: 32 kbyte rom, 512 byte ram h8/3713: 24 kbyte rom, 384 byte ram h8/3712: 16 kbyte rom, 384 byte ram 2 table 1-1 features (cont) item description timers timer a: 8-bit interval timer count-up timer with selection of eight internal clock signals divided from the system clock ( f ) * and four clock signals divided from the subclock ( f sub ) timer b: 8-bit reload timer count-up timer with selection of seven internal clock signals or event input from pin p1 0 /irq 0 timer c: 8-bit reload timer count-up/count-down timer with selection of seven internal clock signals or event input from pin p1 1 /irq 1 timer d: 8-bit event counter up-counter for counting input from pin p1 6 / event timer e: 8-bit reloadable timer count-up timer with selection of eight internal clock signals. square-wave (50% duty cycle) output with a fixed frequency or variable frequency controlled by timer e overflow can be selected by pin p1 5 /irq 5 /tmoe settings. note: * f indicates a clock frequency that is divided in half from the original oscillator frequency 14-bit pwm pulse-division pwm designed for less ripple can be used as a 14-bit d/a converter by connecting to an external low- pass filter vfd up to 24 segment pins and up to 16 digit pins (of which 8 are for both driver/controller uses) brightness adjustable in 8 steps (dimmer function) digit and segment pins can be switched to use as general-purpose high- voltage pins key scan interval can be enabled or disabled interrupt can be requested when key scan interval starts 2-channel synchronous sci1 and sci2 choice of 8-bit or 16-bit data transfer (sci1) automatic transfer of 32-byte data (sci2) overrun error detection possible interrupt can be requested when transfer is complete serial communica- tion interface 3 table 1-1 features (cont) item description a/d converter successive approximations using a resistance ladder resolution: 8 bits 8-channel analog input port conversion time: 31/ f or 62/ f per channel interrupt can be requested at completion of a/d conversion i/o ports high-voltage i/o pins: 32 high-voltage input pin: 1 standard-voltage i/o pins: 12 standard-voltage input pins: 9 interrupts four external interrupt pins: irq 5 , irq 4 , irq 1 , irq 0 ten internal interrupt sources sleep mode standby mode watch mode subactive mode other built-in pulse generators for system clock and subclock timer a can run on the subclock for use as a time base product lineup product code mask rom version ztat ? version package rom/ram size hd6433714h HD6473714h 64 pin gfp rom: 32 kbytes (fp-64a) ram: 512 bytes hd6433714p HD6473714p 64 pin sdip (dp-64s) hd6433713h 64 pin qfp rom: 24 kbytes (fp-64a) ram: 384 bytes hd6433713p 64 pin sdip (dp-64s) hd6433712h 64 pin qfp rom: 16 kbytes (fp-64a) ram: 384 bytes hd6433712p 64 pin sdip (dp-64s) low power operation modes 4 1.2 internal block diagram figure 1-1 is an internal block diagram of the h8/3714 series. figure 1-1 block diagram p6 /fd /fs p6 /fd /fs p6 /fd /fs p6 /fd /fs p6 /fd /fs p6 /fd /fs p6 /fd /fs p6 /fd /fs p9 /pwm p9 /sck p9 /si p9 /so p9 /sck p9 /si /cs p9 /so p9 /ud 0 1 2 3 1 1 1 2 4 52 2 6 7 p5 /fs p5 /fs p5 /fs p5 /fs p5 /fs p5 /fs p5 /fs p5 /fs 0 1 2 3 4 5 15 14 13 12 11 10 9 8 6 7 p4 /fs p4 /fs p4 /fs p4 /fs p4 /fs p4 /fs p4 /fs p4 /fs 0 1 2 3 4 5 16 17 18 19 20 21 22 23 6 7 p1 /irq p1 /irq p1 /irq p1 /irq p1 /irq p1 /irq /tmoe p1 /event p1 /v 0 1 2 3 4 5 6 7 0 1 2 3 4 5 disp 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 7 6 5 4 3 2 1 0 p7 /fd p7 /fd p7 /fd p7 /fd p7 /fd p7 /fd p7 /fd p7 /fd 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 p0 /an p0 /an p0 /an p0 /an p0 /an p0 /an p0 /an p0 /an 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 x x 1 2 osc osc 1 2 test res v cc v ss cpu h8/300l mask rom (prom) subclock pulse generator system clock pulse generator port 5 port 9 port 4 port 6 port 1 port 7 data bus (lower) ram timer a timer b timer c timer d timer e 14-bit pwm sci1 sci2 vfd controller/driver a/d converter port 0 data bus (upper) address bus av av cc ss 5 1.3 pin arrangement and functions 1.3.1 pin arrangement the pin arrangements for the h8/3714 series are shown in figure 1-2 (fp-64a) and figure 1-3 (dp-64s). figure 1-2 pin arrangement (fp-64a: top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 av p0 /an p0 /an p0 /an p0 /an p0 /an p0 /an p0 /an p0 /an av test x x v osc osc 0 1 2 3 4 5 6 7 cc 0 1 2 3 4 5 6 7 ss 2 1 ss 1 2 p7 /fd p6 /fd /fs p6 /fd /fs p6 /fd /fs p6 /fd /fs p6 /fd /fs p6 /fd /fs p6 /fd /fs p6 /fd /fs p1 /v p5 /fs p5 /fs p5 /fs p5 /fs p5 /fs p5 /fs 0 7 6 5 4 3 2 1 0 7 7 6 5 4 3 2 disp 8 7 6 5 4 3 2 1 0 8 9 10 11 12 13 0 1 2 3 4 5 6 7 p9 /ud p9 /so p9 /si /cs p9 /sck p9 /so p9 /si p9 /sck p9 /pwm v p7 /fd p7 /fd p7 /fd p7 /fd p7 /fd p7 /fd p7 /fd 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 cc 2 2 2 1 1 1 15 14 13 12 11 10 9 res p1 /irq p1 /irq p1 /irq p1 /irq /tmoe p1 /event p4 /fs p4 /fs p4 /fs p4 /fs p4 /fs p4 /fs p4 /fs p4 /fs p5 /fs p5 /fs 0 1 4 0 1 4 23 22 21 20 19 18 17 16 15 14 5 5 6 7 6 5 4 3 2 1 0 0 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 6 figure 1-3 pin arrangement (dp-64s: top view) p4 /fs p4 /fs p4 /fs p4 /fs p4 /fs p4 /fs p4 /fs p7 /fd p7 /fd p7 /fd p7 /fd p7 /fd p7 /fd p7 /fd p7 /fd p6 /fd /fs p6 /fd /fs p6 /fd /fs p6 /fd /fs p6 /fd /fs p6 /fd /fs p6 /fd /fs p6 /fd /fs p1 /v p5 /fs p5 /fs p5 /fs p5 /fs p5 /fs p5 /fs p5 /fs p5 /fs 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0 1 2 3 4 5 6 7 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 disp res p1 /irq p1 /irq p1 /irq p1 /irq /tmoe p1 /event p4 /fs v p9 /pwm p9 /sck p9 /si p9 /so p9 /sck p9 /si /cs p9 /so p9 /ud av p0 /an p0 /an p0 /an p0 /an p0 /an p0 /an p0 /an p0 /an av test x x v osc osc 0 cc 1 1 1 2 2 cc 0 1 2 3 4 5 6 7 ss 2 1 ss 1 2 0 1 4 23 1 2 3 4 52 6 7 0 1 2 3 4 5 6 7 0 1 4 5 5 6 7 7 1.3.2 pin functions 1. list of pin functions table 1-2 lists the pin functions of the lsi. table 1-2 list of pin functions pin no. fp-64a dp-64s name and function prom mode 615p0 4 /an 4 (standard input port/analog input channel) nc 716p0 5 /an 5 (standard input port/analog input channel) nc 817p0 6 /an 6 (standard input port/analog input channel) nc 918p0 7 /an 7 (standard input port/analog input channel) nc 10 19 av ss (reference voltage for a/d converter) v ss 11 20 test (test pin) v cc 12 21 x 2 (subclock oscillator connection) nc 13 22 x 1 (subclock oscillator connection) v cc 14 23 v ss (ground) v ss 15 24 osc 1 (system clock oscillator connection) v ss 16 25 osc 2 (system clock oscillator connection) nc 17 26 res (reset input) v pp 18 27 p1 0 /irq 0 (standard i/o port/external interrupt or nc timer b event input) 19 28 p1 1 /irq 1 (standard i/o port/external interrupt or nc timer c event input) 20 29 p1 4 /irq 4 (standard i/o port/external interrupt) nc 21 30 p1 5 /irq 5 /tmoe (standard i/o port/external nc interrupt/warning tone output) 22 31 p1 6 / event (standard input port/timer d event input) ea 9 23 32 p4 7 /fs 23 (high-voltage i/o port/vfd segment output) nc 24 33 p4 6 /fs 22 (high-voltage i/o port/vfd segment output) nc 25 34 p4 5 /fs 21 (high-voltage i/o port/vfd segment output) nc 26 35 p4 4 /fs 20 (high-voltage i/o port/vfd segment output) nc 27 36 p4 3 /fs 19 (high-voltage i/o port/vfd segment output) v cc 28 37 p4 2 /fs 18 (high-voltage i/o port/vfd segment output) v cc 29 38 p4 1 /fs 17 (high-voltage i/o port/vfd segment output) v ss 8 table 1-2 list of pin functions (cont) pin no. fp-64a dp-64s name and function prom mode 30 39 p4 0 /fs 16 (high-voltage i/o port/vfd segment output) v ss 31 40 p5 0 /fs 15 (high-voltage i/o port/vfd segment output) ea 0 32 41 p5 1 /fs 14 (high-voltage i/o port/vfd segment output) ea 1 33 42 p5 2 /fs 13 (high-voltage i/o port/vfd segment output) ea 2 34 43 p5 3 /fs 12 (high-voltage i/o port/vfd segment output) ea 3 35 44 p5 4 /fs 11 (high-voltage i/o port/vfd segment output) ea 4 36 45 p5 5 /fs 10 (high-voltage i/o port/vfd segment output) ea 5 37 46 p5 6 /fs 9 (high-voltage i/o port/vfd segment output) ea 6 38 47 p5 7 /fs 8 (high-voltage i/o port/vfd segment output) ea 7 39 48 p1 7 /v disp (high-voltage input port/vfd power source) v cc 40 49 p6 0 /fd 0 /fs 7 (high-voltage i/o port/vfd digit-segment nc output) 41 50 p6 1 /fd 1 /fs 6 (high-voltage i/o port/vfd digit-segment nc output) 42 51 p6 2 /fd 2 /fs 5 (high-voltage i/o port/vfd digit-segment nc output) 43 52 p6 3 /fd 3 /fs 4 (high-voltage i/o port/vfd digit-segment nc output) 44 53 p6 4 /fd 4 /fs 3 (high-voltage i/o port/vfd digit-segment nc output) 45 54 p6 5 /fd 5 /fs 2 (high-voltage i/o port/vfd digit-segment nc output) 46 55 p6 6 /fd 6 /fs 1 (high-voltage i/o port/vfd digit-segment nc output) 47 56 p6 7 /fd 7 /fs 0 (high-voltage i/o port/vfd digit-segment nc output) 48 57 p7 0 /fd 8 (high-voltage i/o port/vfd digit output) ea 8 49 58 p7 1 /fd 9 (high-voltage i/o port/vfd digit output) oe 50 59 p7 2 /fd 10 (high-voltage i/o port/vfd digit output) ea 10 9 table 1-2 list of pin functions (cont) pin no. fp-64a dp-64s name and function prom mode 51 60 p7 3 /fd 11 (high-voltage i/o port/vfd digit output) ea 11 52 61 p7 4 /fd 12 (high-voltage i/o port/vfd digit output) ea 12 53 62 p7 5 /fd 13 (high-voltage i/o port/vfd digit output) ea 13 54 63 p7 6 /fd 14 (high-voltage i/o port/vfd digit output) ea 14 55 64 p7 7 /fd 15 (high-voltage i/o port/vfd digit output) ce 56 1 v cc (system power source) v cc 57 2 p9 0 /pwm (standard i/o port/pwm output) eo 0 58 3 p9 1 /sck 1 (standard i/o port/clock output) eo 1 59 4 p9 2 /si 1 (standard i/o port/data input) eo 2 60 5 p9 3 /so 1 (standard i/o port/data output) eo 3 61 6 p9 4 /sck 2 (standard i/o port/clock i/o) eo 4 62 7 p9 5 /si 2 / cs (standard i/o port/data input/chip eo 5 select output) 63 8 p9 6 /so 2 (standard i/o port/data output) eo 6 64 9 p9 7 /ud (standard i/o port/timer c up-down control) eo 7 110av cc (reference power source for a/d converter) v cc 211po 0 /an 0 (standard input port/analog input channel) nc 312po 1 /an 1 (standard input port/analog input channel) nc 413po 2 /an 2 (standard input port/analog input channel) nc 514po 3 /an 3 (standard input port/analog input channel) nc notes: 1. nc pins should be left unconnected. 2. details on prom mode are given in 4.2, prom mode. 10 2. pin functions table 1-3 explains the functions of each pin in more detail. table 1-3 pin functions pin no. type symbol fp-64a dp-64s i/o name and functions power v cc 56 1 input power source: connects to a power supply pins supply (+5 v) all v cc pins should be connected to the system power supply (+5 v). v ss 14 23 input ground: connects to a power supply (0 v). all v ss pins should be connected to the system power supply (0 v). av cc 1 10 input analog power supply: this is the reference power supply pin for the a/d converter. when the a/d converter is not used, connect this pin to the system power supply (+5 v). av ss 10 19 input analog ground: this is the a/d converter ground pin. it should be connected to the system power supply (0 v). v disp 39 48 input vfd power supply: this pin should be connected to a vfd driver power supply. clock pins osc 1 15 24 input this pin connects to a crystal or ceramic oscillator, or can be used to input an external clock. see section 6, clock pulse generators, for a typical connection diagram. osc 2 16 25 output this pin connects to a crystal or ceramic oscillator. x 1 13 22 input this pin connects to a 32.768 khz crystal oscillator. for a typical connection diagram, see section 6, clock pulse generators. x 2 12 21 output this pin connects to a 32.768 khz crystal oscillator. 11 table 1-3 pin functions (cont) pin no. type symbol fp-64a dp-64s i/o name and functions system control res 17 26 input reset: when this pin goes to low level, the chip is reset. test 11 20 input test: this pin is not for use in application systems. it should be connected to v ss . interrupt pins irq 0 18 27 input external interrupt request 0: this is an input pin for external interrupts for which there is a choice between rising and falling edge sensing. it can be used to exit low-power mode. this pin can be used as the event input pin for timer b. a noise cancel function is also provided. irq 1 19 28 input external interrupt request 1: this is an input pin for external interrupts for which there is a choice between rising and falling edge sensing. it can be used to exit low-power mode. this pin can be used as the event input pin for timer c. irq 4 20 29 input external interrupt request 4: this is an input pin for external interrupts for which there is a choice between rising and falling edge sensing. irq 5 21 30 input external interrupt request 5: this is an input pin for external interrupts that are detected at the falling edge. 12 table 1-3 pin functions (cont) pin no. type symbol fp-64a dp-64s i/o name and functions timer pins irq 0 18 27 input timer b event counter input: this is an event input pin for input to the timer b counter. irq 1 19 28 input timer c event counter input: this is an event input pin for input to the timer c counter. ud 64 9 input timer c up/down select: this pin selects whether the timer c counter is used for up- or down-counting. at high level it selects down-counting, and at low level up-counting. input to this pin is valid only when bit tmc6 in timer mode register c (tmc) is set to 1. event 22 31 input timer d event counter input: this is an event input pin for input to the timer d counter. tmoe 21 30 output timer e output: this is an output pin for waveforms generated by the timer e output circuit. 14-bit pwm pin pwm 57 2 output 14-bit pwm output: this is an output pin for waveforms generated by the 14-bit pwm. so 1 60 5 output serial transmit data output (channels 1 so 2 63 8 and 2): these are sci data output pins. si 1 59 4 input serial receive data input (channels 1 si 2 62 7 and 2): these are sci data input pins. sck 1 58 3 i/o serial clock i/o (channels 1 and 2): sck 2 61 6 these are sci clock i/o pins. cs 62 7 output chip select output: when sci2 is in transmit mode and the serial clock is an internal clock, this pin goes low. this function is valid when bit si2 in port mode register 2 (pmr2) is 1 and the cs bit in pmr3 is 1. serial communication interface (sci) pins 13 table 1-3 pin functions (cont) pin no. type symbol fp-64a dp-64s i/o name and functions i/o ports p0 7 to 9 to 2 18 to 11 input port 0: this is an 8-bit input port. p0 0 p1 7 39 48 input port 1 (bit 7): this is a 1-bit high- voltage input pin. p1 6 22 31 input port 1 (bit 6): this is a 1-bit input pin. p1 5 , p1 4 , 21 to 18 30 to 27 i/o port 1: this is a 4-bit group of i/o pins. p1 1 , p1 0 input or output can be designated for each bit by means of port control register 1 (pcr1). p4 7 to 23 to 30 32 to 39 i/o port 4: this is an 8-bit high-voltage i/o p4 0 port. p5 7 to 38 to 31 47 to 40 i/o port 5: this is an 8-bit high-voltage i/o p5 0 port. p6 7 to 47 to 40 56 to 49 i/o port 6: this is an 8-bit high-voltage i/o p6 0 port. p7 7 to 55 to 48 64 to 57 i/o port 7: this is an 8-bit high-voltage i/o p7 0 port. p9 7 to 64 to 57 9 to 2 i/o port 9: this is an 8-bit i/o port. input or p9 0 output can be designated for each bit by means of pcr9. a/d converter an 7 to 9 to 2 18 to 11 input analog input channels 7 to 0: these an 0 are analog data input channels to the a/d converter. vfd controller/ fd 15 to 55 to 40 64 to 49 output vfd digit output: these are digit output driver fd 0 pins from the vfd controller/driver. 23 to 38 32 to 47 i/o vfd segment output: these are 40 to 47 49 to 56 segment output pins from the vfd controller/driver. when a key scan interval is set during display operations, these pins can be used by the cpu during this interval as general-purpose i/o ports. fs 23 to fs 8 fs 7 to fs 0 14 section 2 cpu 2.1 overview the h8/300l cpu has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. its concise, optimized instruction set is designed for high-speed operation. 2.1.1 features the main features of the h8/300l cpu are listed below. general-register architecture sixteen 8-bit general registers, also usable as eight 16-bit general registers instruction set with 55 basic instructions, including: multiply and divide instructions powerful bit-manipulation instructions eight addressing modes register direct rn register indirect @rn register indirect with displacement @(d:16, rn) register indirect with post-increment or pre-decrement @rn+ or @?n absolute address @aa:8 or @aa:16 immediate #xx:8 or #xx:16 program-counter relative @(d:8, pc) memory indirect @@aa:8 64-kbyte address space high-speed operation all frequently used instructions are executed in two to four states high-speed arithmetic and logic operations 8- or 16-bit register-register add or subtract: 0.5 ?* ? 8-bit multiply: 3.5 ?* 16 8-bit divide: 3.5 ?* low-power operation modes sleep instruction for transfer to low-power operation note: * these values are at f = 4 mhz. 15 2.1.2 address space the h8/300l cpu supports an address space of up to 64 kbytes for storing program code and data. the memory map varies with the rom size. figure 2-1 gives memory map. figure 2-1 memory map h'0000 h'002b h'3fff h'5fff h'7dff h'fd80 h'fe00 h'ffc0 h'feff h'ff00 h'ff7f h'ff80 h'ff9f h'ffa0 h'ffa3 h'ffa4 h'ffaf h'ffb0 h'ffff interrupt vectors (44 bytes) on-chip rom on-chip ram used also for vfd display ram (64 bytes) on-chip ram (128 bytes) 32-byte data buffer internal i/o registers (4 bytes) reserved internal i/o registers (80 bytes) h8/3712 h8/3713 h8/3714 16 kbytes (16,384) 24 kbytes (24,576) 32 kbytes (32,256) 384 bytes 384 bytes 512 bytes reserved 16 2.1.3 register configuration figure 2-2 shows the register structure of the h8/300l cpu. there are two groups of registers: the general registers and control registers. figure 2-2 cpu registers 7070 15 0 pc r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l (sp) sp: stack pointer pc: program counter ccr: condition code register carry flag overflow flag zero flag negative flag half-carry flag interrupt mask bit user bit user bit ccr i u h u n z v c general registers (rn) control registers 753210 64 17 2.2 register descriptions 2.2.1 general registers all the general registers can be used as both data registers and address registers. when used as data registers, they can be accessed as 16-bit registers (r0 to r7), or the high bytes (r0h to r7h) and low bytes (r0l to r7l) can be accessed separately as 8-bit registers. when used as address registers, the general registers are accessed as 16-bit registers (r0 to r7). r7 also functions as the stack pointer (sp), used implicitly by hardware in exception processing and subroutine calls. when it functions as the stack pointer, as indicated in figure 2-3, sp (r7) points to the top of the stack. figure 2-3 stack pointer 2.2.2 control registers the cpu control registers include a 16-bit program counter (pc) and an 8-bit condition code register (ccr). 1. program counter (pc): this 16-bit register indicates the address of the next instruction the cpu will execute. all instructions are fetched 16 bits (1 word) at a time, so the least significant bit of the pc is ignored (always regarded as 0). 2. condition code register (ccr): this 8-bit register contains internal status information, including the interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. lower address side [h'0000] upper address side [h'ffff] unused area stack area sp (r7) 18 bit 7?nterrupt mask bit (i): when this bit is set to 1, interrupts are masked. this bit is set to 1 automatically at the start of exception handling. the interrupt mask bit may be read and written by software. for further details, see 3.2.2, interrupts. bit 6?ser bit (u): can be written and read by software (using the ldc, stc, andc, orc, and xorc instructions). bit 5?alf-carry flag (h): when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0 otherwise. the h flag is used implicitly by the daa and das instructions. when the add.w, sub.w, or cmp.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and is cleared to 0 otherwise. bit 4?ser bit (u): can be written and read by software (using the ldc, stc, andc, orc, and xorc instructions). bit 3?egative flag (n): indicates the most significant bit (sign bit) of the result of an instruction. bit 2?ero flag (z): set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. bit 1?verflow flag (v): set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. bit 0?arry flag (c): set to 1 when a carry occurs, and cleared to 0 otherwise. used by: add instructions, to indicate a carry subtract instructions, to indicate a borrow shift and rotate instructions, to store the value shifted out of the end bit the carry flag is also used as a bit accumulator by bit manipulation instructions. some instructions leave some or all of the flag bits unchanged. the ldc, stc, andc, orc, and xorc instructions enable the cpu to load and store the ccr, and to set or clear selected bits by logic operations. the n, z, v, and c flags are used as branching conditions for conditional branching (bcc) instructions. refer to the h8/300l series programming manual for the action of each instruction on the flag bits. 19 2.2.3 initial register values when the cpu is reset, the program counter (pc) is initialized to the value stored at address h'0000 in the vector table, and the i bit in the ccr is set to 1. the other ccr bits and the general registers are not initialized. in particular, the stack pointer (r7) is not initialized. to prevent program crashes the stack pointer should be initialized by software, by the first instruction executed after a reset. 2.3 data formats the h8/300l cpu can process 1-bit data, 4-bit (bcd) data, 8-bit (byte) data, and 16-bit (word) data. bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand (n = 0, 1, 2, ..., 7). all arithmetic and logic instructions except adds and subs can operate on byte data. the mov.w, add.w, sub.w, cmp.w, adds, subs, mulxu (8 bits 8 bits), and divxu (16 bits 8 bits) instructions operate on word data. the daa and das instructions perform decimal arithmetic adjustments on byte data in packed bcd form. each nibble of the byte is treated as a decimal digit. 20 2.3.1 data formats in general registers data of all the sizes above can be stored in general registers as shown in figure 2-4. figure 2-4 register data formats 76543210 don? care data type register no. data format 70 1-bit data rnh 76543210 don? care 70 1-bit data rnl msb lsb don? care 70 byte data rnh byte data rnl word data rn 4-bit bcd data rnh 4-bit bcd data rnl notation: rnh: rnl: msb: lsb: upper digit of general register lower digit of general register most significant bit least significant bit msb lsb don? care 70 msb lsb 15 0 upper digit lower digit don? care 70 3 4 don? care upper digit lower digit 70 3 4 21 2.3.2 memory data formats figure 2-5 indicates the data formats in memory. for access by the h8/300l cpu, word data stored in memory must always begin at an even address. in word access the least significant bit of the address is regarded as 0. if an odd address is specified, the access is performed at the preceding even address. this rule affects the mov.w instruction, and also applies to instruction fetching. word access is possible to the rom and ram areas. for details, see 2.8.1, notes on data access. figure 2-5 memory data formats when the stack is accessed using r7 as an address register, word access should always be performed. for further details, see 3.2.10, notes on stack area use. when the ccr is pushed on the stack, two identical copies of the ccr are pushed to make a complete word. when they are restored, the lower byte is ignored. data format 76543210 address data type 70 address n msb lsb msb lsb upper 8 bits lower 8 bits msb lsb ccr ccr * msb lsb msb lsb address n even address odd address even address odd address even address odd address 1-bit data byte data word data byte data (ccr) on stack word data on stack note: * ignored on return notation: ccr: condition code register 22 2.4 addressing modes 2.4.1 addressing modes the h8/300l cpu supports the eight addressing modes listed in table 2-1. each instruction uses a subset of these addressing modes. table 2-1 addressing modes no. address modes symbol 1 register direct rn 2 register indirect @rn 3 register indirect with displacement @(d:16, rn) 4 register indirect with post-increment @rn+ register indirect with pre-decrement @?n 5 absolute address @aa:8 or @aa:16 6 immediate #xx:8 or #xx:16 7 program-counter relative @(d:8, pc) 8 memory indirect @@aa:8 1. register direct?n: the register field of the instruction specifies an 8- or 16-bit general register containing the operand. only the mov.w, add.w, sub.w, cmp.w, adds, subs, mulxu (8 bits 8 bits), and divxu (16 bits 8 bits) instructions have 16-bit operands. 2. register indirect?rn: the register field of the instruction specifies a 16-bit general register containing the address of the operand. 3. register indirect with displacement?(d:16, rn): the instruction has a second word (bytes 3 and 4) containing a displacement which is added to the contents of the specified general register to obtain the operand address. this mode is used only in mov instructions. for the mov.w instruction, the resulting address must be even. 23 4. register indirect with post-increment or pre-decrement?rn+ or @?n: register indirect with post-increment?rn+ the @rn+ mode is used with mov instructions that load registers from memory. the register field of the instruction specifies a 16-bit general register containing the address of the operand. after the operand is accessed, the register is incremented by 1 for mov.b or 2 for mov.w. for mov.w, the original contents of the 16-bit general register must be even. register indirect with pre-decrement??n the @?n mode is used with mov instructions that store register contents to memory. the register field of the instruction specifies a 16-bit general register which is decremented by 1 or 2 to obtain the address of the operand in memory. the register retains the decremented value. the size of the decrement is 1 for mov.b or 2 for mov.w. for mov.w, the original contents of the register must be even. 5. absolute address?aa:8 or @aa:16: the instruction specifies the absolute address of the operand in memory. the absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). the mov.b and bit manipulation instructions can use 8-bit absolute addresses. the mov.b, mov.w, jmp, and jsr instructions can use 16-bit absolute addresses. for an 8-bit absolute address, the upper 8 bits are assumed to be 1 (h'ff). the address range is h'ff00 to h'ffff (65280 to 65535). 6. immediate?xx:8 or #xx:16: the instruction contains an 8-bit operand (#xx:8) in its second byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. only mov.w instructions can contain 16-bit immediate values. the adds and subs instructions implicitly contain the value 1 or 2 as immediate data. some bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the instruction, specifying a bit number. 7. program-counter relative?(d:8, pc): this mode is used in the bcc and bsr instructions. an 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits and added to the program counter contents to generate a branch destination address. the possible branching range is ?26 to +128 bytes (?3 to +64 words) from the current address. the displacement should be an even number. 24 8. memory indirect?@aa:8: this mode can be used by the jmp and jsr instructions. the second byte of the instruction code specifies an 8-bit absolute address. the word located at this address contains the branch destination address. the upper 8 bits of the absolute address are assumed to be 0 (h'00), so the address range is from h'0000 to h'00ff (0 to 255). note that with the h8/3714 series, addresses h'0000 to h'002b (0 to 43) are located in the vector table. if an odd address is specified as a branch destination or as the operand address of a mov.w instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. see 2.3.2, memory data formats, for further information. 2.4.2 effective address calculation table 2-2 shows how effective addresses are calculated in each of the addressing modes. arithmetic and logic instructions use register direct addressing (1). the add.b, addx, subx, cmp.b, and, or, and xor instructions can also use immediate addressing (6). data transfer instructions can use all addressing modes except program-counter relative (7) and memory indirect (8). bit manipulation instructions use register direct (1), register indirect (2), or absolute addressing (5) to specify a byte operand, and 3-bit immediate addressing (6) to specify a bit position in that byte. the bset, bclr, bnot, and btst instructions can also use register direct addressing (1) to specify the bit position. 25 table 2-2 effective address calculation addressing mode and instruction format op rm 76 3 40 15 no. effective address calculation method effective address (ea) 1 register direct, rn operand is contents indicated by rm/rn. register indirect, @rn contents (16 bits) of register indicated by rm 0 15 register indirect with displacement, @(d:16, rn) op rm rn 87 3 40 15 op rm 76 3 40 15 disp op rm 76 3 40 15 register indirect with post-increment, @rn+ op rm 76 3 40 15 register indirect with pre-decrement, @?n 2 3 4 incremented or decremented by 1 if operand is byte size, and by 2 if word size. 0 15 disp 0 15 0 15 0 15 1 or 2 0 15 0 15 1 or 2 0 15 rm 30 rn 30 contents (16 bits) of register indicated by rm contents (16 bits) of register indicated by rm contents (16 bits) of register indicated by rm 26 table 2-2 effective address calculation (cont) addressing mode and instruction format no. effective address calculation method effective address (ea) 5 absolute address @aa:8 operand is 1- or 2-byte immediate data. @aa:16 op 87 0 15 op 0 15 imm op disp 70 15 program-counter relative @(d:8, pc) 6 7 0 15 pc contents 0 15 0 15 abs h'ff 87 0 15 0 15 abs op #xx:16 op 87 0 15 imm immediate #xx:8 8 sign extension disp 27 table 2-2 effective address calculation (cont) addressing mode and instruction format no. effective address calculation method effective address (ea) 8 memory indirect, @@aa:8 op 87 0 15 memory contents (16 bits) 0 15 abs h'00 87 0 15 notation: rm, rn: op: disp: imm: abs: register field operation field displacement immediate data absolute address abs 28 2.5 instruction set the h8/300l cpu can use a total of 55 instructions, which are grouped by function in table 2-3. table 2-3 instruction set function instructions types data transfer mov, push * 1 , pop * 1 1 arithmetic operations add, sub, addx, subx, inc, dec, adds, 14 subs, daa, das, mulxu, divxu, cmp, neg logic operations and, or, xor, not 4 shift shal, shar, shll, shlr, rotl, rotr, 8 rotxl, rotxr bit manipulation bset, bclr, bnot, btst, band, biand, bor, 14 bior, bxor, bixor, bld, bild, bst, bist branch bcc * 2 , jmp, bsr, jsr, rts 5 system control rte, sleep, ldc, stc, andc, orc, xorc, nop 8 block data transfer eepmov 1 total: 55 notes: 1. push rn is equivalent to mov.w rn, @?p. pop rn is equivalent to mov.w @sp+, rn. 2. bcc is the generic designation of a conditional branch instruction. the following sections give a concise summary of the instructions in each category, and indicate the bit patterns of their object code. the notation used is defined next. 29 notation rd general register (destination) rs general register (source) rn general register (ead) 2.5.1 data transfer instructions table 2-4 describes the data transfer instructions. figure 2-6 shows their object code formats. table 2-4 data transfer instructions instruction size * function mov b/w (eas) ? rd, rs ? (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. the rn, @rn, @(d:16, rn), @aa:16, #xx:8 or #xx:16, @?n, and @rn+ addressing modes are available for byte or word data. the @aa:8 addressing mode is available for byte data only. the @?7 and @r7+ modes require word operands. do not specify byte size for these two modes. push w rn ? @?p pushes a 16-bit general register onto the stack. equivalent to mov.w rn, @?p. pop w @sp+ ? rn pops a 16-bit general register from the stack. equivalent to mov.w @sp+, rn. notes: * size: operand size b: byte w: word certain precautions are required in data access. see 2.8.1, notes on data access, for details. 31 figure 2-6 data transfer instruction codes 15 0 87 op rm rn mov rm ? rn 15 0 87 op rm rn @rm ?? rn 15 0 87 op rm rn @(d:16, rm) ?? rn disp 15 0 87 op rm rn @rm+ ? rn, or rn ? @?m 15 0 87 op rn abs @aa:8 ?? rn 15 0 87 op rn @aa:16 ?? rn abs 15 0 87 op rn imm #xx:8 ? rn 15 0 87 op rn #xx:16 ? rn imm 15 0 87 op rn push, pop notation: op: rm, rn: disp: abs: imm: operation field register field displacement absolute address immediate data @sp+ rn, or rn @?p ? ? 111 32 2.5.2 arithmetic operations table 2-5 describes the arithmetic instructions. see figure 3-6 in section 3.5.4, shift operations for their object codes. table 2-5 arithmetic instructions instruction size * function add b/w rd rs ? rd, rd + #imm ? rd sub performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. immediate data cannot be subtracted from data in a general register. word data can be added or subtracted only when both words are in general registers. addx b rd rs c ? rd, rd #imm c ? rd subx performs addition or subtraction with carry or borrow on byte data in two general registers, or addition or subtraction on immediate data and data in a general register. inc b rd 1 ? rd dec increments or decrements a general register. adds w rd 1 ? rd, rd 2 ? rd subs adds or subtracts immediate data to or from data in a general register. the immediate data must be 1 or 2. b rd decimal adjust ? rd decimal-adjusts (adjusts to packed bcd) an addition or subtraction result in a general register by referring to the ccr. mulxu b rd rs ? rd performs 8-bit 8-bit unsigned multiplication on data in two general registers, providing a 16-bit result. divxu b rd rs ? rd performs 16-bit 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder. cmp b/w rd ?rs, rd ?#imm compares data in a general register with data in another general register or with immediate data, and sets the ccr according to the result. word data can be compared only between two general registers. neg b 0 ?rd ? rd obtains the two s complement (arithmetic complement) of data in a general register. notes: * size: operand size b: byte w: word daa das 33 2.5.3 logic operations table 2-6 describes the four instructions that perform logic operations. table 2-6 logic operation instructions instruction size * function and b rd rs ? rd, rd #imm ? rd performs a logical and operation on a general register and another general register or immediate data. or b rd rs ? rd, rd #imm ? rd performs a logical or operation on a general register and another general register or immediate data. xor b rd ? rs ? rd, rd ? #imm ? rd performs a logical exclusive or operation on a general register and another general register or immediate data. not b ~ rd ? rd obtains the one s complement (logical complement) of general register contents. notes: * size: operand size b: byte 2.5.4 shift operations table 2-7 describes the eight shift instructions. table 2-7 shift instructions instruction size * function b rd shift ? rd performs an arithmetic shift operation on general register contents. b rd shift ? rd performs a logical shift operation on general register contents. b rd rotate ? rd rotates general register contents. b rd rotate through carry ? rd rotates general register contents through the c (carry) bit. notes: * size: operand size b: byte shal shar shll shlr rotl rotr rotxl rotxr 34 figure 2-7 shows the instruction code format of arithmetic, logic, and shift instructions. figure 2-7 arithmetic, logic, and shift instruction codes 15 0 87 op rm rn add, sub, cmp, addx, subx (rm) notation: op: rm, rn: imm: operation field register field immediate data 15 0 87 op rn adds, subs, inc, dec, daa, das, neg, not 15 0 87 op rn mulxu, divxu rm 15 0 87 rn imm add, addx, subx, cmp (#xx:8) op 15 0 87 op rn and, or, xor (rm) rm 15 0 87 rn imm and, or, xor (#xx:8) op 15 0 87 rn shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr op 35 2.5.5 bit manipulations table 2-8 describes the bit-manipulation instructions. figure 2-8 shows their object code formats. table 2-8 bit-manipulation instructions instruction size * function bset b 1 ? ( table 2-8 bit-manipulation instructions (cont) instruction size * function bxor b c ? ( figure 2-8 bit manipulation instruction codes 15 0 87 op imm rn operand: bit no.: notation: op: rm, rn: abs: imm: operation field register field absolute address immediate data 15 0 87 op rn bset, bclr, bnot, btst register direct (rn) immediate (#xx:3) operand: bit no.: register direct (rn) register direct (rm) rm 15 0 87 op 0 operand: bit no.: register indirect (@rn) immediate (#xx:3) rn 0 0 0 0 0 0 0 imm 15 0 87 op 0 operand: bit no.: register indirect (@rn) register direct (rm) rn 0 0 0 0 0 0 0 rm op 15 0 87 op operand: bit no.: absolute (@aa:8) immediate (#xx:3) abs 0000 imm op op 15 0 87 op operand: bit no.: absolute (@aa:8) register direct (rm) abs 0000 rm op 15 0 87 op imm rn operand: bit no.: register direct (rn) immediate (#xx:3) band, bor, bxor, bld, bst 15 0 87 op 0 operand: bit no.: register indirect (@rn) immediate (#xx:3) rn 0 0 0 0 0 0 0 imm op 15 0 87 op operand: bit no.: absolute (@aa:8) immediate (#xx:3) abs 0000 imm op 38 figure 2-8 bit manipulation instruction codes (cont) notation: op: rm, rn: abs: imm: operation field register field absolute address immediate data 15 0 87 op imm rn operand: bit no.: register direct (rn) immediate (#xx:3) biand, bior, bixor, bild, bist 15 0 87 op 0 operand: bit no.: register indirect (@rn) immediate (#xx:3) rn 0 0 0 0 0 0 0 imm op 15 0 87 op operand: bit no.: absolute (@aa:8) immediate (#xx:3) abs 0000 imm op 39 2.5.6 branching instructions table 2-9 describes the branching instructions. table 2-9 branching instructions instruction size function bcc branches to the designated address if condition cc is true. the branching conditions are given below. mnemonic description condition bra (bt) always (true) always brn (bf) never (false) never bhi high c z = 0 bls low or same c z = 1 bcc (bhs) carry clear (high or same) c = 0 bcs (blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n ? v = 0 blt less than n ? v = 1 bgt greater than z (n ? v) = 0 ble less or equal z (n ? v) = 1 jmp branches unconditionally to a specified address. jsr branches to a subroutine at a specified address. bsr branches to a subroutine at a specified displacement from the current address. rts returns from a subroutine. 40 figure 2-9 branching instruction codes notation: op: cc: rm: disp: abs: operation field condition field register field displacement absolute address 15 0 87 op cc disp bcc 15 0 87 op rm 0 jmp (@rm) 000 15 0 87 op jmp (@aa:16) abs 15 0 87 op abs jmp (@@aa:8) 15 0 87 op disp bsr 15 0 87 op rm 0 jsr (@rm) 000 15 0 87 op jsr (@aa:16) abs 15 0 87 op abs jsr (@@aa:8) 15 0 87 op rts 41 2.5.7 system control instructions table 2-10 describes the system control instructions. figure 2-10 shows their object code formats. table 2-10 system control instructions instruction size * function rte returns from an exception-handling routine. sleep causes a transition from active mode to a power-down mode (sleep mode, standby mode, or watch mode), or from subactive mode to watch mode, or from subactive mode via watch mode to active mode. for details, see 3.3, system modes. ldc b rs ? ccr, #imm ? ccr moves immediate data or general register contents to the condition code register. stc b ccr ? rd copies the condition code register to a specified general register. andc b ccr #imm ? ccr logically ands the condition code register with immediate data. orc b ccr #imm ? ccr logically ors the condition code register with immediate data. xorc b ccr ? #imm ? ccr logically exclusive-ors the condition code register with immediate data. nop pc + 2 ? pc only increments the program counter. notes: * size: operand size b: byte 42 figure 2-10 system control instruction codes 2.5.8 block data transfer instruction table 2-11 describes the block data transfer instruction. figure 2-11 shows its object code format. table 2-11 block data transfer instruction instruction size function eepmov if r4l 0 then repeat @r5+ ? @r6+ r4l ?1 ? r4l until r4l = 0 else next; moves a data block according to parameters set in general registers r4l, r5, and r6. r4l: size of block (bytes) r5: starting source address r6: starting destination address execution of the next instruction starts as soon as the block transfer is completed. notation: op: rn: imm: operation field register field immediate data 15 0 87 op rte, sleep, nop 15 0 87 op rn ldc, stc (rn) 15 0 87 op imm andc, orc, xorc, ldc (#xx:8) 43 figure 2-11 block data transfer instruction code notes on eepmov instruction 1. the eepmov instruction is a block data transfer instruction. it moves the number of bytes specified by r4l from the address specified by r5 to the address specified by r6. 2. when setting r4l and r6, make sure that the final destination address (r6 + r4l) does not exceed h'ffff. the value in r6 must not change from h'ffff to h'0000 during execution of the instruction. notation: op: operation field 15 0 87 op op ? r6 ? r6 + r4l r5 ? r5 + r4l ? h'ffff not allowed ? r6 ? r6 + r4l r5 ? r5 + r4l ? 44 2.6 cpu states 2.6.1 overview there are three cpu states: program execution state, program halt state, and exception-handling state. program execution state includes active mode and subactive mode. in program halt state there are sleep mode, standby mode, and watch mode. these states are shown in figure 2-12. figure 2-13 shows the state transitions. figure 2-12 cpu operation states state program execution state active mode subactive mode the cpu executes successive program instructions, synchronized by the system clock. the cpu executes successive program instructions at reduced speed, synchronized by the subclock. program halt state a state in which cpu operations are stopped to conserve power. exception- handling state a transient state in which the cpu changes the processing flow due to a reset or an interrupt. sleep mode standby mode watch mode low-power operation modes 45 figure 2-13 state transitions 2.6.2 program execution state in the program execution state the cpu executes program instructions in sequence. there are two modes in this state, active mode and subactive mode. operation is synchronized with the system clock in active mode, and with a subclock in subactive mode. for details on these modes, see 3.3, system modes. 2.6.3 program halt state in the program halt state there are three modes: sleep mode, standby mode, and watch mode. for details on these modes, see 3.3, system modes. 2.6.4 exception-handling state the exception-handling state is a transient state occurring when exception handling is started by a reset or interrupt, and the cpu changes its normal processing flow. in exception handling caused by an interrupt, sp (r7) is referenced and the pc and ccr values are saved on the stack. for details on interrupt handling, see 3.2.2, interrupts. reset state program halt state exception-handling state program execution state reset cleared sleep instruction executed reset occurs interrupt reset occurs exception- handling request exception- handling ends note: on the transitions between modes, see 3.3, system modes. reset occurs 46 2.7 basic operation timing cpu operation is synchronized by a clock ( f i ). f i is either the system clock ( f ) generated by the system clock oscillator circuit, or the subclock ( f sub ) generated by the subclock oscillator circuit. f i denotes f in active mode and f sub in subactive mode. for details, see section 6, clock pulse generators. the period from the rising edge of f i to the next rising edge is called one state. a memory cycle or bus cycle consists of two states; access to on-chip memory and to on-chip peripheral modules always takes place in two states. 2.7.1 access to on-chip memory (ram, rom) two-state access is employed for on-chip memory. the data bus width is 16 bits, allowing access in byte or word size. figure 2-14 shows the on-chip memory access cycle. figure 2-14 on-chip memory access cycle t 1 state bus cycle t 2 state f internal address bus internal read signal internal data bus (read access) internal write signal read data address write data internal data bus (write access) i 47 2.7.2 access to on-chip peripheral modules on-chip peripheral modules are accessed in two states. the data bus width is 8 bits, so access is made in byte size only. this means that two instructions must be used for a word size data access. figure 2-15 shows the on-chip peripheral module access cycle. figure 2-15 on-chip peripheral module access cycle t 1 state bus cycle t 2 state f internal address bus internal read signal internal data bus (read access) internal write signal read data address write data internal data bus (write access) i 48 2.8 application notes the following points are to be observed in using the h8/300l cpu. 2.8.1 notes on data access 1. the address space of the h8/300l cpu includes some empty areas in addition to the ram, registers, and rom areas available to the user. if these empty areas are mistakenly accessed by an application program, the following results will occur. transfer from cpu to empty area: the transferred data will be lost. this action may also cause the cpu to misoperate. transfer from empty area to cpu: unpredictiable data is transferred. 2. internal data transfer to or from on-chip modules other than rom and ram areas makes use of an 8-bit data width. if word access is attempted to these areas, the following results will occur. word access from cpu to i/o register area: upper byte: will be written to i/o register. lower byte: transferred data will be lost. word access from i/o register to cpu: upper byte: will be written to upper part of cpu register. lower byte: data written to lower part of cpu register cannot be guaranteed. byte size instructions should therefore be used when transferring data to or from i/o registers outside the on-chip rom and ram areas. figure 2-16 shows the data size in which access can be made with on-chip peripheral modules. 49 figure 2-16 data size for access to and from on-chip peripheral modules 512 bytes * 2 32,256 bytes * 1 h'0000 h'002b h'7dff * 1 interrupt vector area (44 bytes) on-chip rom on-chip ram (320 bytes) on-chip ram (128 bytes) 32-byte data buffer internal i/o registers (4 bytes) reserved internal i/o registers (80 bytes) h'fd80 * 2 h'fec0 h'ff00 h'ff7f h'ff80 h'ff9f h'ffa0 h'ffa3 h'ffa4 h'ffaf h'ffb0 h'ffff used also for vfd display ram (64 bytes) access word byte : access possible : not possible notes: the above example is a description of the h8/3714. 1. 2. the h8/3713 has 24,576 bytes of on-chip rom, and its ending address is h'5fff. the h8/3712 has 16,384 bytes of on-chip rom, and its ending address is h'3fff. the h8/3713 and h8/3712 each have 384 bytes of on-chip ram, and their ending address is h'fe00. 50 2.8.2 notes on bit manipulation the h8/300l cpu executes bit manipulation instructions by a read-modify-write operation on 8-bit data. when bit manipulation instructions are executed in the cases illustrated below, care must be taken since the operation may affect other bits besides those being manipulated. 1. bit manipulation in two registers assigned to the same address (when the source and destination are different) example 1: timer load register and timer counter in this example, a bit manipulation instruction is executed in the timer load register and timer counter of a reloadable timer. since the timer load register and timer counter share the same address, the operations take place as follows. a. read: the timer counter value at the time is read. b. modify: the cpu modifies (sets or resets) the bit designated with the instruction. (other bits remain the same.) c. write: the modified data is written to the timer load register. the timer counter is counting based on the system clock ( f ), so the value read is not necessarily the same as the value in the timer load register. as a result, bits other than the intended bit in the timer load register may be modified to the timer counter value. figure 2-17 shows the reloadable timer configuration. figure 2-17 reloadable timer configuration example 2: port data register (pin input and data register) when a bit manipulation instruction is executed designating a port data register, it may cause changes in pin i/o states or data register contents other than the intended bit. f r: w: timer counter reload internal bus timer load register read write r w 51 as noted above, the h8/300l cpu executes bit manipulation instructions by a read-modify-write operation on 8-bit data. since the same address is used for the i/o port data register and reading of pin input, a bit manipulation instruction designating a port functions as follows. ? high-voltage pin: pin other than the modified bit when set as an input pin (data register = 0) first the cpu reads the pin input level (read), then it sets or resets the designated bit (modify; other bits remain the same), and writes that value to the data register (write). if the input level is high (read data = 1), a value of 1 is written to the data register, changing the input pin to an output pin (high-level output). if the input level is low, no change occurs. when set as an output pin (data register = 1, high-level output) if the output level is higher than the input high level (v ih ), there is no change. if the output level is lower than the input low level (v il ), a value of 0 is written to the data register, so that the pmos buffer transistor is turned off resulting in pull-down (low level) or high-impedance state. if the output level is pulled down by the load to an intermediate level, the resulting state is indeterminate. - standard-voltage pin: pin other than the modified bit when set as an input pin the cpu reads the pin input level and writes that value to the data register, which may or may not result in a change to the data register contents. when set as an output pin the data register is read, so no change occurs. 2. bit manipulation in registers containing write-only bits example: pwm data registers, etc. (note that read and write characteristics can differ from bit to bit.) write-only bits cannot be read. write-only bits other than the intended bit are set to 1. 52 table 2-12 lists the registers that share the same address, while table 2-13 lists the registers that contain write-only bits. table 2-12 registers assigned to the same address register name abbreviation address timer load register b/timer counter b tlb/tcb h'ffc3 timer load register c/timer counter c tlc/tcc h'ffc5 timer load register e/timer counter e tle/tce h'ffc9 port data register 1 * pdr1 h'ffd1 port data register 4 * pdr4 h'ffd4 port data register 5 * pdr5 h'ffd5 port data register 6 * pdr6 h'ffd6 port data register 7 * pdr7 h'ffd7 port data register 9 * pdr9 h'ffd9 note: * these port data registers are used also for pin input. table 2-13 registers with write-only bits register name abbreviation address serial mode register 1 smr1 h'ffb0 pwm control register pwcr h'ffcc pwm data register u pwdru h'ffcd pwm data register l pwdrl h'ffce port control register 1 pcr1 h'ffe1 port control register 9 pcr9 h'ffe9 port mode register 0 pmr0 h'ffef timer mode register d * 1 tmd h'ffc6 system control register 2 * 2 syscr2 h'fff1 notes: 1. only bit crl (bit 7) is write-only. 2. bit dton (bit 3) is a write-only bit only in subactive mode. in active mode it cannot be read or written. 53 54 section 3 system control 3.1 overview this section explains the reset state, exception handling, and system modes. 3.2 exception handling exception handling includes processing of reset exceptions and of interrupts. table 3-1 summarizes the exception sources and their priorities. reset exception handling has the highest priority. table 3-1 types of exception handling and priorities priority exception source timing for start of exception handling high reset reset exception handling starts as soon as res pin changes from low to high. interrupt when interrupt request is made, interrupt exception handling low starts after execution of present instruction is completed. 3.2.1 reset when the res pin goes low, all processing stops and the chip enters the reset state. the internal state of the cpu and the registers of on-chip peripheral modules are initialized. the i bit of the condition code register (ccr) is set, masking all interrupts. as soon as the res pin goes from low to high, reset exception handling starts. the contents of the reset vector address (h'0000 to h'0001) are read and loaded into the program counter (pc). then program execution starts from the address indicated in pc. figure 3-1 shows the reset sequence. notes: 1. to make sure a reset is carried out properly, when power is turned on the res pin should be kept low for at least 20 ms after the rise of the power supply. 2. when resetting during operation, keep the res pin low for at least 10 system clock cycles. 3. after a reset, if an interrupt were to be accepted before the stack pointer (sp: r7) was initialized, pc and ccr would not be pushed onto the stack correctly, resulting in program runaway. to prevent this, immediately after reset exception handling all interrupts are masked. programs should be coded to initialize the stack pointer before clearing the interrupt mask. an even-numbered address must be set in sp. it is recommended that programs start with an instruction initializing sp (e.g., mov.w #xx:16, sp). 55 figure 3-1 reset sequence 3.2.2 interrupts the interrupt sources include external interrupts (irq 5 , irq 4 , irq 1 , irq 0 ), and internal interrupts requested from on-chip peripheral modules. table 3-2 shows the interrupt sources, their priorities, and their vector addresses. when more than one interrupt is requested, the interrupt with the highest priority is processed. the interrupts have the following features. both internal interrupts and external interrupts (irq 5 , irq 4 , irq 1 , irq 0 ), can be masked by the i bit of ccr. when this bit is set to 1, interrupt request flags are set but interrupts are not accepted. external interrupt pins irq 4 , irq 1 , and irq 0 can be set independently for rising-edge or falling-edge sensing. for external interrupt pin irq 5 , the falling edge is sensed. vector fetch f internal address bus internal read signal internal write signal internal data bus (16 bits) res internal processing prefetch of first instruction of program (1) reset exception handling vector address (h'0000) (2) program starting address (3) first instruction of program (2) (1) (3) (2) reset state reset exception handling and program execution 56 table 3-2 interrupt sources vector starting priority interrupt origin of interrupt address high reset external pin h'0000 (reserved) * 1 h'0002 h'0004 h'0006 irq 0 external pin h'0008 irq 1 h'000a (reserved) * 1 h'000c (reserved) * 1 h'000e irq 4 h'0010 irq 5 h'0012 key scan vfd h'0014 timer a overflow timer a h'0016 timer b overflow timer b h'0018 timer c overflow timer c h'001a timer d overflow timer d h'001c timer e overflow timer e h'001e direct transfer standby timer activator * 2 h'0020 (reserved) * 1 h'0022 h'0024 sci1 transfer complete, error serial communication interface 1 h'0026 sci2 transfer complete, error serial communication interface 2 h'0028 low a/d conversion end a/d converter h'002a notes: 1. vector addresses indicated as ?eserved?cannot be used. 2. this circuit is triggered by a sleep instruction and generates an interrupt after a certain time. 57 3.2.3 interrupt control registers table 3-3 lists the registers that are used to control interrupts. table 3-3 interrupt control registers register name abbreviation r/w initial value address port mode register 1 pmr1 r/w h'0c h'ffeb irq edge select register iegr r/w h'ec h'fff2 interrupt enable register 1 ienr1 r/w h'c0 h'fff3 interrupt enable register 2 ienr2 r/w h'00 h'fff4 interrupt enable register 3 ienr3 r/w h'3c h'fff5 interrupt request register 1 irr1 r/w * h'c0 h'fff6 interrupt request register 2 irr2 r/w * h'00 h'fff7 interrupt request register 3 irr3 r/w * h'3c h'fff8 note: * write is enabled only for writing of 0 to clear flag. 1. port mode register 1 (pmr1) pmr1 is an 8-bit read/write register that designates whether pins in port 1 are used for general- purpose i/o or for external interrupt input. it is also used to turn the noise canceller function of pin irq 0 on or off. note: before switching a pin function by modifying bit irq5, irq4, irq1, or irq0 in pmr1, first clear the interrupt enable flag to disable the interrupt. after the pin function has been switched, issue any instruction, then clear the interrupt request flag to 0. program example: mov. b r0l, @ienr1 ...................... disable interrupt mov. b r0l, @pmr1 ...................... change pin function nop ...................... issue any instruction mov. b r0l, @irr1 ...................... clear interrupt request flag mov. b r1l, @ienr1 ...................... enable interrupt bit initial value read/write 7 0 r/w 6 event 0 r/w 5 irqc5 0 r/w 4 irqc4 0 r/w 3 1 0 irqc0 0 r/w 2 1 1 irqc1 0 r/w noise cancel 58 bit 7: noise cancel (noise cancel) this bit enables or disables the noise canceller function of pin irq 0 . bit 7 noise cancel description 0 disables the noise canceller function of pin irq 0 . (initial value) 1 enables the noise canceller function of pin irq 0 . input is sampled at intervals of 256 states. if two consecutive values do not match, the input is regarded as noise. bit 6: p1 6 / event pin function switch (event) bit 6 event description 0p1 6 / event pin functions as p1 6 pin. (initial value) 1p1 6 / event pin functions as event pin. bit 5: p1 5 /irq 5 /tmoe pin function switch (irqc5) bit 5 irqc5 description 0p1 5 /irq 5 /tmoe pin functions as p1 5 /tmoe pin. * (initial value) 1p1 5 /irq 5 /tmoe pin functions as irq 5 pin. note: * for the tmoe usage of this pin, see 7.3.2, port mode register 4 . bit 4: p1 4 /irq 4 pin function switch (irqc4) bit 4 irqc4 description 0p1 4 /irq 4 pin functions as p1 4 pin. (initial value) 1p1 4 /irq 4 pin functions as irq 4 pin. bits 3 and 2: reserved bits bits 3 and 2 are reserved; they always read 1, and cannot be modified. 59 bit 1: p1 1 /irq 1 pin function switch (irqc1) bit 1 irqc1 description 0p1 1 /irq 1 pin functions as p1 1 pin. (initial value) 1p1 1 /irq 1 pin functions as irq 1 pin. bit 0: p1 0 /irq 0 pin function switch (irqc0) bit 0 irqc0 description 0p1 0 /irq 0 pin functions as p1 0 pin. (initial value) 1p1 0 /irq 0 pin functions as irq 0 pin. 2. irq edge select register (iegr) iegr is an 8-bit read/write register, used to designate rising edge sensing or falling edge sensing for pins irq 0 , irq 1 , and irq 4 . bits 7 to 5: reserved bits bits 7 to 5 are reserved; they always read 1, and cannot be modified. bit 4: irq 4 pin input edge select (ieg4) bit 4 ieg4 description 0 falling edge of irq 4 pin input is detected. (initial value) 1 rising edge of irq 4 pin input is detected. bits 3 and 2: reserved bits bits 3 and 2 are reserved; they always read 1, and cannot be modified. bit initial value read/write 7 1 6 1 5 1 4 ieg4 0 r/w 3 1 0 ieg0 0 r/w 2 1 1 ieg1 0 r/w 60 bit 1: irq 1 pin input edge select (ieg1) bit 1 ieg1 description 0 falling edge of irq 1 pin input is detected. (initial value) 1 rising edge of irq 1 pin input is detected. bit 0: irq 0 pin input edge select (ieg0) bit 0 ieg0 description 0 falling edge of irq 0 pin input is detected. (initial value) 1 rising edge of irq 0 pin input is detected. 3. interrupt enable register 1 (ienr1) ienr1 is an 8-bit read/write register that enables or disables external interrupts. bits 7 and 6: reserved bits bits 7 and 6 are reserved; they always read 1, and cannot be modified. bits 5 and 4: irq 5 and irq 4 interrupt enable (ien5 and ien4) bits 5 and 4 ien5, ien4 description 0 disables interrupt requests by irri5 and irri4. (initial value) 1 enables interrupt requests by irri5 and irri4. bits 3 and 2: reserved bits bits 3 and 2 are reserved, but they can be written and read. bits 1 and 0: irq 1 and irq 0 interrupt enable (ien1 and ien0) bits 1 and 0 ien1, ien0 description 0 disables interrupt requests by irri1 and irri0. (initial value) 1 enables interrupt requests by irri1 and irri0. bit initial value read/write 7 1 6 1 5 ien5 0 r/w 4 ien4 0 r/w 3 0 r/w 0 ien0 0 r/w 2 0 r/w 1 ien1 0 r/w 61 4. interrupt enable register 2 (ienr2) ienr2 is an 8-bit read/write register that enables or disables direct transfer interrupts and timer a to e overflow interrupts. bits 7 and 6: reserved bits bits 7 and 6 are reserved, but they can be written and read. bit 5: direct transfer interrupt enable (iendt) bit 5 iendt description 0 disables direct transfer interrupt requests by irrdt. (initial value) 1 enables interrupt requests by irrdt. bits 4 to 0: timer e to a interrupt enable (iente to ienta) bits 4 to 0 iente to ienta description 0 disables interrupt requests by irrte to irrta. (initial value) 1 enables interrupt requests by irrte to irrta. 5. interrupt enable register 3 (ienr3) ienr3 is an 8-bit read/write register that enables or disables a/d converter, key scan, and serial communication interface 1 and 2 interrupts. bit initial value read/write 7 0 r/w 6 0 r/w 5 iendt 0 r/w 4 iente 0 r/w 3 ientd 0 r/w 0 ienta 0 r/w 2 ientc 0 r/w 1 ientb 0 r/w bit initial value read/write 7 ienad 0 r/w 6 ienks 0 r/w 5 1 4 1 3 1 0 iens1 0 r/w 2 1 1 iens2 0 r/w 62 bit 7: a/d converter interrupt enable (ienad) bit 7 ienad description 0 disables interrupt requests by irrad. (initial value) 1 enables interrupt requests by irrad. bit 6: key scan interrupt enable (ienks) bit 6 ienks description 0 disables interrupt requests by irrks. (initial value) 1 enables interrupt requests by irrks. bits 5 to 2: reserved bits bits 5 to 2 are reserved; they always read 1, and cannot be modified. bits 1 and 0: serial communication interface 2 and 1 interrupt enable (iens2 and iens1) bits 1 and 0 iens2, iens1 description 0 disables interrupt requests by irrs2 and irrs1. (initial value) 1 enables interrupt requests by irrs2 and irrs1. 6. interrupt request register 1 (irr1) note: * only 0 can be written, to clear the flag. irr1 is an 8-bit read/write register with flags that are set to 1 when an external interrupt is requested. bits 7 and 6: reserved bits bits 7 and 6 are reserved; they always read 1, and cannot be modified. bit initial value read/write 7 1 6 1 5 irri5 0 r/w 4 irri4 0 r/w 3 0 0 irri0 0 r/w 2 0 1 irri1 0 r/w ** ** 63 bits 5 and 4: irq 5 and irq 4 interrupt request (irri5 and irri4) bits 5 and 4 irri5, irri4 description 0 no interrupt request from the corresponding pin (irq 5 or irq 4 ). (initial value) 1 setting condition: set when the corresponding pin (irq 5 or irq 4 ) is designated for interrupt input in pmr1 and the designated edge is input. clearing method: cleared when software writes 0 in the flag. (the flag is not automatically cleared when an interrupt is accepted.) bits 3 and 2: reserved bits bits 3 and 2 are reserved; they always read 0, and cannot be modified. bits 1 and 0: irq 1 and irq 0 interrupt request (irri1 and irri0) bits 1 and 0 irri1, irri0 description 0 no interrupt request from the corresponding pin (irq 1 or irq 0 ). (initial value) 1 setting condition: set when the corresponding pin (irq 1 or irq 0 ) is designated for interrupt input in pmr1 and the designated edge is input. clearing method: cleared when software writes 0 in the flag. (the flag is not automatically cleared when an interrupt is accepted.) 7. interrupt request register 2 (irr2) note: * only 0 can be written, to clear the flag. irr2 is an 8-bit read/write register with flags that are set to 1 when a direct transfer interrupt or timer a to e overflow interrupt is requested. bits 7 and 6: reserved bits bits 7 and 6 are reserved; they always read 0, and only 0 may be written. bit initial value read/write 7 0 6 0 5 irrdt 0 r/w 4 irrte 0 r/w 3 irrtd 0 r/w 0 irrta 0 r/w 2 irrtc 0 r/w 1 irrtb 0 r/w * *** ** 64 bit 5: direct transfer interrupt request (irrdt) bits 5 irrdt description 0 no direct transfer interrupt request. (initial value) 1 setting conditions: in subactive mode, when the system control register 2 (syscr2) dton bit = 1, the system control register 1 (syscr1) lson bit = 0, and the interrupt enable register 2 (ienr2) iendt bit = 1, execution of a sleep instruction results in direct transfer to active mode via watch mode. during this process a direct transfer interrupt is requested and the irrdt flag is set to 1. clearing method: cleared when software writes 0 in the flag. (the flag is not automatically cleared when an interrupt is accepted.) bits 4 to 0: timer e to a interrupt request (irrte to irrta) bits 4 to 0 irrte to irrta description 0 no overflow interrupt request from the corresponding timer (initial value) (e to a). 1 setting conditions: when a timer e to a overflow interrupt is requested, the corresponding flag (irrte to irrta ) is set to 1. clearing method: cleared when software writes 0 in the flag. (the flag is not automatically cleared when an interrupt is accepted.) 8. interrupt request register 3 (irr3) note: * only 0 can be written, to clear the flag. bit 7: a/d conversion complete interrupt request (irrad) bit 7 irrad description 0 no a/d converter interrupt request. (initial value) 1 setting conditions: when the a/d converter completes a/d conversion, an interrupt is requested and the irrad flag is set to 1. clearing method: cleared when software writes 0 in the flag. (the flag is not automatically cleared when an interrupt is accepted.) bit initial value read/write 7 irrad 0 r/w 6 irrks 0 r/w 5 1 4 1 3 1 0 irrs1 0 r/w 2 1 1 irrs2 0 r/w ** ** 65 bit 6: key scan interrupt request (irrks) bit 6 irrks description 0 no key scan interrupt request. (initial value) 1 setting conditions: when the vfd controller/driver requests a key scan interrupt, the irrks flag is set to 1. clearing method: cleared when software writes 0 in the flag. (the flag is not automatically cleared when an interrupt is accepted.) bits 5 to 2: reserved bits bits 5 to 2 are reserved; they always read 1, and cannot be modified. bits 1 and 0: serial communication interface 2 and 1 interrupt request (irrs2, irrs1) bits 1, 0 irrs2, irrs1 description 0 no transfer complete or error interrupt request by the (initial value) corresponding serial communication interface. 1 setting conditions: when an interrupt is requested due to transfer complete or error on serial communication interface 2 or 1, the corresponding flag (irrs2 or irrs1) is set to 1. clearing method: cleared when software writes 0 in the flag. (the flag is not automatically cleared when an interrupt is accepted.) 3.2.4 external interrupts there are four external interrupts, irq 5 , irq 4 , irq 1 , and irq 0 . these interrupts are requested by means of input signals at pins irq 5 , irq 4 , irq 1 , and irq 0 . interrupts irq 4 , irq 1 , and irq 0 are detected by either rising edge sensing or falling edge sensing, depending on the settings of bits ieg4, ieg1, and ieg0 in the irq edge select register (iegr). irq 5 is detected by falling edge sensing only. in order to enable external interrupt input, it is first necessary to set the corresponding bit in port mode register 1 (pmr1) to 1. when the designated edge is input at pins irq 5 , irq 4 , irq 1 , and irq 0 , the corresponding flag in interrupt request register 1 (irr1) is set to 1. after the interrupt is accepted, the flag that was set is not automatically cleared, so the interrupt handling routine must be programmed to clear the flag to 0. a given interrupt request can be disabled by clearing its interrupt enable bit to 0. interrupts irq 5 , irq 4 , irq 1 , and irq 0 are enabled by setting bits ien5, ien4, ien1, and ien0 to 1 in interrupt enable register 1. all interrupts can be masked by setting the i bit in ccr to 1. 66 when an irq 5 , irq 4 , irq 1 , or irq 0 interrupt request is accepted, the i bit is set to 1. the order of priority is from irq 0 (high) to irq 5 (low). for details see table 3-2. a noise canceller function can be selected for irq 0 interrupts, in which case a noise cancellation circuit samples the irq 0 input every 256 states. if two consecutive sampling results do not match, noise is assumed and the request is not accepted. 3.2.5 internal interrupts there are ten internal interrupts that can be requested by the on-chip peripheral modules. these interrupts can be masked (held pending) by setting the i bit in ccr to 1. when an internal interrupt request is accepted and the interrupt exception handling sequence is executed, the i bit is set to 1. for the order of priority of interrupts from on-chip peripheral modules, see table 3-2. 3.2.6 interrupt operations interrupts are controlled by an interrupt controller. figure 3-2 shows a block diagram of the interrupt controller, while figure 3-3 shows the flow up to interrupt acceptance. figure 3-2 block diagram of interrupt controller interrupt controller priority decision interrupt request ccr (cpu) i irq , iqr , irq , and irq interrupt request flags and internal interrupt request flags 5 0 41 irq , iqr , irq , and irq interrupt enable bits and internal interrupt enable bits 5 0 41 67 figure 3-3 flow up to interrupt acceptance pc contents saved ccr contents saved i ? 1 branch to interrupt handling routine i = 0 pending interrupt request? irq 4 sci2 program execution state no yes yes no yes no yes no yes no yes notation: pc: ccr: i: program counter condition code register i bit of ccr a/d yes irq 0 irq 1 no 14 interrupts 68 the following operations take place when an interrupt occurs. 1. when an interrupt is requested by external interrupt pin input or by a peripheral module, an interrupt request signal is sent to the interrupt controller. 2. when the interrupt controller receives an interrupt request signal, it sets the interrupt request flag. 3. from among the interrupts for which the corresponding interrupt enable bit is also set to 1, the interrupt controller selects the interrupt request with the highest priority and holds the others pending. (see table 3-2.) 4. the interrupt controller checks the i bit of ccr. if the i bit is 0, the selected interrupt request is accepted; if the i bit is 1, the interrupt request is held pending. 5. if the interrupt is accepted, after processing of the current instruction is completed, both pc and ccr are pushed onto the stack. the state of the stack at this time is shown in figure 3-4. the pc value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling. 6. the i bit of ccr is set to 1, masking all further interrupts. 7. a vector address is generated for the accepted interrupt, and the contents of that address are read and loaded into pc. program execution then resumes from the address indicated in pc. note: no interrupt detection takes place immediately after completion of orc, andc, xorc, or ldc instructions. 69 figure 3-4 stack state after completion of interrupt exception handling figure 3-5 shows a typical interrupt sequence. contents saved to stack sp (r7) sp ?1 sp ?2 sp ?3 sp ?4 stack area sp + 4 sp + 3 sp + 2 sp + 1 sp (r7) even address prior to start of interrupt exception handling after completion of interrupt exception handling notation: pc h : pc l : ccr: sp: upper 8 bits of program counter (pc) lower 8 bits of program counter (pc) condition code register stack pointer * ignored on return from interrupt. notes: 1. 2. ccr ccr * pc h pc l pc shows the address of the first instruction to be executed upon return from the interrupt. saving and restoring of register contents must always be done in word size, and must start from an even-numbered address. 70 figure 3-5 interrupt sequence vector fetch f internal address bus internal read signal internal write signal (2) internal data bus (16 bits) interrupt request signal (9) (1) internal processing prefetch instruction of interrupt-handling routine (1) instruction prefetch address (instruction is not executed. address is saved as pc contents, becoming return address.) (2)(4) instruction code (not executed) (3) instruction prefetch address (instruction is not executed.) (5) sp ?2 (6) sp ?4 (7) ccr (8) vector address (9) starting address of interrupt-handling routine (contents of vector) (10) first instruction of interrupt-handling routine (3) (9) (8) (6) (5) (4) (1) (7) (10) stack access internal processing instruction prefetch interrupt level decision and wait for end of instruction interrupt is accepted 71 3.2.7 return from an interrupt after completion of interrupt handling, the handler routine ends by executing an rte instruction, to resume the original program from the point the interrupt. when rte is executed, the values saved on the stack are restored to ccr and pc as shown in figure 3-6. instruction execution resumes from the address indicated in pc. figure 3-6 stack state when rte instruction is executed 3.2.8 interrupt response time table 3-4 shows the number of wait states after an interrupt request flag is set and until the first instruction of the interrupt handler is executed. table 3-4 interrupt wait states no. item states 1 waiting time for completion of current instruction * 1 to 13 2 saving of pc and ccr to stack 4 3 vector fetch 2 4 instruction fetch 4 5 internal processing 4 total 15 to 27 note: * not including eepmov instruction. (processing of rte instruction) (stack state) memory contents of address indicated in sp are sent to ccr. sp value +2 memory contents of address indicated in sp are sent to pc. sp value +2 ccr ccr * sp (r7) sp + 1 sp + 2 sp + 3 sp + 4 sp ?4 sp ?3 sp ?2 sp ?1 sp (r7) pc h pc l ccr ccr * pc h pc l stack area stack area ccr and pc values restored before rte instruction is executed after rte instruction is executed * ignored on return from interrupt. note: 72 3.2.9 valid interrupts in each mode table 3-5 shows the valid interrupts in each mode. for details of the modes, see 3.3, system modes. table 3-5 valid interrupts in each mode mode interrupt active sleep standby watch subactive irq 0 mmmmm irq 1 mmm irq 4 m irq 5 m key scan m timer a overflow mm mm timer b overflow m timer c overflow m timer d overflow m timer e overflow m direct transfer d sci1 transfer complete or error m sci2 transfer complete or error m a/d conversion end m note: the above table does not include interrupts occurring during a mode transition. notation: m : when an interrupt request flag is set, interrupt exception handling is started if the i bit = 0 in ccr and the interrupt enable bit = 1 for that interrupt. in sleep mode, standby mode, and watch mode, a mode transition takes place before interrupt exception handling starts. d : when a sleep instruction is executed while the dton bit = 1 and the lson bit = 0, first a transition is made to watch mode and the interrupt request flag is set in synchronization with the subclock. when the interrupt request flag is set, if the interrupt enable flag = 1 for that interrupt and the i bit = 0 in ccr, a transition is made to active mode and interrupt exception handling starts. : the interrupt request flag is not set, and no mode transition occurs. 73 3.2.10 notes on stack area use when word data is accessed in the h8/300l series, the least significant bit of the address is regarded as 0. access to the stack always takes place in word size, so the stack pointer (sp: r7) should never indicate an odd address. use push rn (mov.w rn, @?p) or pop rn (mov.w @sp+, rn) to save or restore register values. setting an odd address in sp may cause a program to crash. an example is shown in figure 3-7. figure 3-7 cpu operation when odd address is set in sp word access is also performed when the condition code register (ccr) is saved and restored by the interrupt exception-handling sequence and rte instruction. when ccr is saved, the ccr value is saved in both the upper and lower bytes of the word data. when ccr is restored, it is loaded with the value at the even address. the value at the odd address is ignored. sp sp set to h'feff sp sp pc l pc l pc h r1l h'fefd h'fefc h'feff stack accessed beyond sp bsr instruction contents of pc are lost h mov.b r1l, @?7 notation: pc h : pc l : r1l: sp: upper byte of program counter lower byte of program counter general register r1l stack pointer 74 3.3 system modes the h8/300l cpu is equipped with power-down modes for minimizing power dissipation. these and the other system modes are described below. there are five modes altogether, as follows. active mode sleep mode standby mode watch mode subactive mode figure 3-8 shows the transitions among these modes. figure 3-8 system mode transition diagram ssby = 0 and sleep instruction sleep mode irq or irq or timer a 01 ssby = 1 and tma3 = 0 and sleep instruction standby mode active mode irq or irq 01 lson = 0 and irq , or lson = 0 and time base 0 * ssby = 1 and tma3 = 1 and sleep instruction lson = 1 and irq 0 , or lson = 1 and time base * dton = 0 and sleep instruction lson = 0 and dton = 1 and sleep instruction subactive mode reset watch mode res res res res res * time base: timer a interrupt during time-base operation running on subclock. note: low-power operation modes 75 3.3.1 active mode in active mode, the cpu executes instructions in synchronization with the system clock. 3.3.2 low-power operation mode the h8/300l cpu supports four low-power operation modes: sleep mode, standby mode, watch mode, and subactive mode. these modes are described below. sleep mode: sleep mode is entered by executing a sleep instruction while the ssby bit in system control register 1 (syscr1) is cleared to 0. as soon as the sleep instruction has been executed, the cpu and on-chip peripheral modules halt operation, except for timer a. the contents of the internal registers of the cpu and on-chip peripheral modules, as well as the ram contents, are retained. standby mode: standby mode is entered by executing a sleep instruction while the ssby bit in system control register 1 (syscr1) is set to 1 and timer mode register a (tma) bit tma3 = 0. in this mode, the cpu, system clock, and on-chip peripheral modules halt all operations. output from the on-chip peripheral modules is reset; but as long as a minimum required voltage is applied, the contents of the internal registers of the cpu and on-chip peripheral modules, as well as the ram contents, are retained. standard i/o ports go to the high- impedance state. in high-voltage ports, the pmos buffer transistors are switched off. watch mode: watch mode is entered by executing a sleep instruction while the ssby bit in system control register 1 (syscr1) is set to 1 and timer mode register a (tma) bit tma3 = 1. in this mode, the cpu, system clock, and on-chip peripheral modules halt, except for timer a. output from the on-chip peripheral modules is reset; but as long as a minimum required voltage is applied, the contents of the internal registers of the cpu and on-chip peripheral modules, as well as the ram contents, are retained. standard i/o ports go to the high-impedance state. in high-voltage ports, the pmos buffer transistors are switched off. subactive mode: subactive mode is entered when a time base or irq 0 interrupt request is accepted in watch mode while the lson bit in system control register 1 (syscr1) is set to 1. in this mode the cpu operates in synchronization with the subclock. on-chip peripheral modules halt operation, except for the time- base function of timer a. output from the on-chip peripheral modules is reset; but as long as a minimum required voltage is applied, the contents of the internal registers of the on-chip peripheral modules are retained. standard i/o ports go to the high-impedance state. in high-voltage ports, the pmos buffer transistors are switched off. 76 table 3-6 shows the internal states in each mode. table 3-6 internal states in operation modes function active sleep standby watch subactive system clock functions functions halted halted halted subclock functions functions functions functions functions cpu operation instructions functions halted halted halted functions ram functions retained retained retained functions registers functions retained retained retained functions i/o functions retained retained * 1 retained * 1 functions * 1, * 2 irq 0 functions functions functions functions functions irq 1 functions functions functions retained retained irq 4 , irq 5 functions retained retained retained retained timer a functions functions retained functions * 3 functions * 3 timer b functions retained retained retained retained timer c functions retained retained retained retained timer d functions retained retained retained retained timer e functions retained retained retained retained sci1, sci2 functions retained retained retained retained vfd functions retained retained retained retained (output is (output is (output is (output is reset) reset) reset) reset) pwm functions retained retained retained retained (output is (output is (output is (output is reset) reset) reset) reset) a/d functions retained retained retained retained notes: 1. register contents are retained; output goes to high-impedance state. 2. input (read) functions. 3. functions when the time base function is selected. peripheral module interrupts 77 1. sleep mode operation in sleep mode is described below. transition to sleep mode the system goes from active mode to sleep mode when a sleep instruction is executed while the ssby bit in system control register 1 (syscr1) is cleared to 0. in this mode cpu operation is halted but the register, ram, and port contents are retained. the clock pulse generator operates, as do external interrupts (irq 1 and irq 0 ) and timer a. clearing sleep mode sleep mode is cleared by an interrupt (irq 1 , irq 0 , or timer a) or by input at the res pin. clearing by interrupt (irq 1 , irq 0 , or timer a) when an irq 1 , irq 0 , or timer a interrupt is requested, sleep mode is cleared and interrupt exception handling starts. sleep mode is not cleared if the i bit in the condition code register (ccr) is set to 1 or the particular interrupt is disabled in the interrupt enable register. before transition to sleep mode, other interrupts should be disabled. clearing by res input when the res pin goes low, the cpu goes into the reset state and sleep mode is cleared. 2. standby mode operation in standby mode is described below. transition to standby mode the system goes from active mode to standby mode when a sleep instruction is executed while the ssby bit in system control register 1 (syscr1) is set to 1 and bit tma3 in timer mode register a (tma) is cleared to 0. in standby mode the clock pulse generator stops, so the cpu and on-chip peripheral modules stop functioning. as long as a minimum required voltage is applied, the cpu register contents and data in the on-chip ram will be retained. standard i/o ports go to the high-impedance state. in high-voltage ports, the pmos buffer transistors are switched off. 78 clearing standby mode standby mode is cleared by an external interrupt (irq 1 , irq 0 ) or by input at the res pin. clearing by interrupt (irq 1 , irq 0 ) when an irq 1 or irq 0 interrupt signal is input, the clock pulse generator starts. after the time set in bits sts2 to sts0 in system control register 1 (syscr1) has elapsed, a stable clock signal is supplied to the entire chip, standby mode is cleared, and interrupt exception handling starts. before the transition to standby mode, other interrupts should be disabled. standby mode is not cleared if the i bit in the condition code register (ccr) is set to 1 or the particular interrupt is disabled in the interrupt enable register. clearing by res input when the res pin goes low, the clock pulse generator starts and standby mode is cleared. after the pulse generator output has stabilized, if the res pin is driven high, the cpu starts reset exception handling. since clock signals are supplied to the entire chip as soon as the clock pulse generator starts functioning, the res pin should be kept at the low level until the pulse generator output stabilizes. 3. watch mode operation in watch mode is described below. transition to watch mode from active mode, watch mode is entered when a sleep instruction is executed while the ssby bit in system control register 1 (syscr1) is set to 1 and bit tma3 in timer mode register a (tma) is set to 1. from subactive mode, watch mode is entered when a sleep instruction is executed while the dton bit in system control register 2 (syscr2) is cleared to 0. in watch mode, operation of the system clock pulse generator and of on-chip peripheral modules is halted, except for the time-base function of timer a. output from the on-chip peripheral modules is reset; but as long as a minimum required voltage is applied, the contents of the internal registers of the cpu and on-chip peripheral modules, and the on-chip ram contents, are retained. 79 clearing watch mode watch mode is cleared by a time-base interrupt from timer a, by an irq 0 interrupt, or by input at the res pin. clearing by timer a time-base interrupt or irq 0 interrupt when timer a overflows or an irq 0 interrupt signal is input, if the lson bit in system control register 1 (syscr1) is cleared to 0, the clock pulse generator starts. after the time set in bits sts2 to sts0 in system control register 1 (syscr1) has elapsed, a stable clock signal is supplied to the entire chip, watch mode is cleared, and interrupt exception handling starts. if lson = 1, the system goes to subactive mode. in watch mode, the subclock ( f sub ) is prescaled to generate a clock signal which is supplied to timer a. timer a operates as a time base. before the transition to watch mode, other external interrupts should be disabled. watch mode is not cleared if the i bit in the condition code register (ccr) is set to 1 or the particular interrupt is disabled in the interrupt enable register. clearing by res input when the res pin goes low, the clock pulse generator starts and watch mode is cleared. after the pulse generator output has stabilized, if the res pin is driven high, the cpu starts reset exception handling. since clock signals are supplied to the entire chip as soon as the clock pulse generator starts functioning, the res pin should be kept at the low level until the pulse generator output stabilizes. 4. subactive mode operation in subactive mode is described below. transition to subactive mode subactive mode is entered from watch mode if the lson bit in system control register 1 (syscr1) is set to 1 at the time of a timer a time-base interrupt or irq 0 interrupt request. in subactive mode, the cpu operates in synchronization with the subclock ( f sub ). the on- chip peripheral modules halt operation, except for the time base function of timer a. output from the on-chip peripheral modules is reset; but as long as a minimum required voltage is applied, the contents of the internal registers of the on-chip peripheral modules are retained. standard i/o ports go to the high-impedance state. in high-voltage ports, the pmos buffer transistors are switched off. 80 clearing subactive mode subactive mode is cleared by a sleep instruction or by input at the res pin. clearing by sleep instruction when a sleep instruction is executed in subactive mode, subactive mode is cleared. if the dton bit of system control register 2 (syscr2) is cleared to 0 when the sleep instruction is executed, the system goes to watch mode. if dton = 1 and lson = 0, a direct transfer interrupt is requested and the clock pulse generator starts. after the time set in bits sts2 to sts0 in system control register 1 (syscr1) has elapsed, a stable clock signal is supplied to the entire chip, and the system goes to active mode. before the transition to active mode, other interrupts should be disabled. the direct transfer from subactive mode to active mode does not take place if the i bit in the condition code register (ccr) is set to 1 or the direct transfer interrupt is disabled in the interrupt enable register. clearing by res input when the res pin goes low, the clock pulse generator starts and subactive mode is cleared. after the pulse generator output has stabilized, if the res pin is driven high, the cpu starts reset exception handling. since clock signals are supplied to the entire chip as soon as the clock pulse generator starts functioning, the res pin should be kept at the low level until the pulse generator output stabilizes. 81 3.3.3 application notes 1. in order to ensure sufficient time for the clock pulse generator to reach stable operation after clearing of standby mode or watch mode, or after a direct transfer from subactive to active mode, bits sts2 to sts0 in system control register 1 (syscr1) should be set as follows. when a ceramic oscillator is used set bits sts2 to sts0 for a waiting time of at least 10 ms (see figure 3-9). for details, see 3.4.1, system control register 1 (syscr1). when an external clock is used any values may be set. normally the minimum time (sts2 = sts1 = sts0 = 0) should be set. figure 3-9 waiting time 2. to make a transition from subactive mode to active mode, the lson bit in syscr1 should be cleared to 0 and the dton bit in system control register 2 (syscr2) should be set to 1. direct transfer is not possible when the lson bit = 1. power-on or standby cleared v t oscillator stabilization time t r waiting time 3 10 ms oscillator waveform 82 3.4 system control registers table 3-7 shows how the system control registers (syscr1 and syscr2) are configured. these two registers are used to control the power-down modes. table 3-7 register configuration name abbreviation r/w initial value address system control register 1 syscr1 r/w h'00 h'fff0 system control register 2 syscr2 r/w h'f4 h'fff1 3.4.1 system control register 1 (syscr1) note: * write is enabled only in active mode. syscr1 is an 8-bit read/write register for control of power-down modes. bit 7: standby (ssby) this bit designates transition to standby mode. when standby mode is cleared by an external interrupt and the system goes to active mode, this bit remains set to 1. it must be cleared by writing a 0. writing is possible only in active mode. bit 7 ssby explanation 0 when a sleep instruction is executed, a transition is made to sleep (initial value) mode. 1 when a sleep instruction is executed, a transition is made to standby mode or watch mode. bit initial value read/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 lson 0 r/w 0 0 2 0 r/w 1 0 * 83 bits 6 to 4: standby timer select 2 to 0 (sts2 to sts0) when a mode in which the system clock is stopped (standby, watch, or subactive mode) is cleared, the system waits for stable clock operation for a time set in these bits. the designation should be made according to the clock frequency so that the waiting time is at least 10 ms. bit 6 bit 5 bit 4 sts2 sts1 sts0 explanation 0 0 0 wait time = 8,192 states. (initial value) 0 0 1 wait time = 16,384 states. 0 1 0 wait time = 32,768 states. 0 1 1 wait time = 65,536 states. 1 ** wait time = 131,072 states. note: * don? care. bit 3: low speed on flag (lson) this bit chooses the system clock ( f ) or subclock ( f sub ) as the cpu operating clock when watch mode is cleared. since this relates to the transitions between operation modes, this bit functions in combination with other control bits and interrupt input. bit 3 lson explanation 0 the cpu operates on the system clock ( f ). (initial value) 1 the cpu operates on the subclock ( f sub ). bit 2: reserved bit this bit is reserved, but it can be written and read. bits 1 and 0: reserved bits these bits are reserved; they always read 0, and cannot be modified. 84 3.4.2 system control register 2 (syscr2) note: * write is enabled only in subactive mode. syscr2 is an 8-bit read/write register for control of direct transfer from subactive mode to active mode. bits 7 to 4: reserved bits these bits are reserved; they always read 1, and cannot be modified. bit 3: direct transfer on flag (dton) this bit designates whether a transition is made to active mode or to watch mode when a sleep instruction is executed in subactive mode. when transfer to active mode is designated, the transition takes place via watch mode to allow time for the clock pulse generator to stabilize. bit 3 dton explanation 0 when a sleep instruction is executed in subactive mode, a transition is (initial value) made to watch mode. 1 when a sleep instruction is executed in subactive mode while the lson bit in system control register 1 (syscr1) is cleared to 0, a direct transfer interrupt is requested, and the system goes to active mode via watch mode. bit 2: reserved bit this bit is reserved; it always reads 1, and cannot be modified. bits 1 and 0: reserved bits these bits are reserved, but they can be written and read. bit initial value read/write 7 1 6 1 5 1 4 1 3 dton 0 w 0 0 r/w 2 1 1 0 r/w * 85 86 section 4 rom 4.1 overview the h8/3714 has 32 kbytes of on-chip mask rom. the h8/3713 has 24 kbytes, and the h8/3712 has 16 kbytes. the rom is connected to the cpu by a 16-bit data bus, allowing high-speed two- state access for both byte data and word data. the ztat version of the h8/3714 has a 32-kbyte prom. 4.1.1 block diagram figure 4-1 gives a block diagram of the on-chip rom. figure 4-1 rom block diagram (h8/3714) internal data bus (upper 8 bits) internal data bus (lower 8 bits) even-numbered addresses odd-numbered addresses h'0000 h'0002 h'0001 h'0003 h'7dfe h'7dff 87 4.2 prom mode 4.2.1 selection of prom mode if the on-chip rom is a prom, setting the chip to prom mode stops operation as a microcontroller and allows the prom to be programmed in the same way as the hn27c256h. table 4-1 shows how to select prom mode. table 4-1 selection of prom mode pin name setting test pin test high level mode pin md 0 (p4 0 /fs 16 ) low level mode pin md 1 (p4 1 /fs 17 ) mode pin md 2 (p1 7 /v disp ) high level 4.2.2 socket adapter pin arrangement and memory map a standard prom programmer can be used to program the prom. a socket adapter is required for conversion to 28 pins, as listed in table 4-2. figure 4-2 shows the pin-to-pin wiring of the socket adapter. figure 4-3 shows a memory map. table 4-2 socket adapter package socket adapter 64-pin (fp-64a) hs3714esh01h 64-pin (dp-64s) hs3714ess01h 88 figure 4-2 socket adapter pin correspondence h8/3714 eprom socket fp-64a 17 57 58 59 60 61 62 63 64 31 32 33 34 35 36 37 38 48 22 50 51 52 53 54 55 49 27 28 39 29 30 56, 1 14, 10 11 15 dp-64s 26 2 3 4 5 6 7 8 9 40 41 42 43 44 45 46 47 57 31 59 60 61 62 63 64 58 36 37 48 38 39 1, 10 23, 19 20, 22 24 pin p9 0 p9 1 p9 2 p9 3 p9 4 p9 5 p9 6 p9 7 p5 0 p5 1 p5 2 p5 3 p5 4 p5 5 p5 6 p5 7 p7 0 p1 6 p7 2 p7 3 p7 4 p7 5 p7 6 p7 7 p7 1 p4 3 p4 2 p1 7 p4 1 p4 0 v cc , av cc v ss , av ss test, x1 osc 1 pin v pp eo 0 eo 1 eo 2 eo 3 eo 4 eo 5 eo 6 eo 7 ea 0 ea 1 ea 2 ea 3 ea 4 ea 5 ea 6 ea 7 ea 8 ea 9 ea 10 ea 11 ea 12 ea 13 ea 14 v cc v ss v cc v ss v cc hn27c256h 1 11 12 13 15 16 17 18 19 10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 20 22 28 28 14 28 14 res ce oe note: pins not indicated above should be left open. v ss 14 89 figure 4-3 memory map in prom mode h'0000 h'7dff h'0000 h'7dff address in mcu mode address in prom mode on-chip rom 90 4.3 programming the write, verify, and other modes are selected as shown in table 4-3 in prom mode. table 4-3 mode selection in prom mode pin mode ce oe v pp v cc eo 7 to eo 0 ea 14 to ea 0 write l h v pp v cc data input address input verify h l v pp v cc data output address input programming disabled h h v pp v cc high impedance address input notation: l: low level h: high level v pp :v pp level v cc :v cc level the specifications for writing and reading the on-chip prom are identical to those for the standard hn27c256h eprom. 4.3.1 writing and verifying an efficient, high-speed programming method is provided for writing and verifying the prom data. this method achieves high speed without voltage stress on the device and without lowering the reliability of written data. h'ff data is written in unused address areas. the basic flow of this high-speed programming method is shown in figure 4-4. table 4-4 and table 4-5 give the electrical characteristics in programming mode. figure 4-5 shows a timing diagram. 91 figure 4-4 high-speed programming flow chart start select write or verify mode v = 6.0 v ?0.25 v, v = 12.5 v ?0.3 v cc pp address = 0 n = 0 n + 1 n ? write with t = 1 ms ?% pw verify write with t = 3n ms opw last address? read all addresses address + 1 address ? error end select read mode v = 5.0 v ?0.5 v, v = v ?0.6 v cc pp cc n < 25 yes no yes no no go go go no go 92 table 4-4 dc characteristics (preliminary) (conditions: v cc = 6.0 v ?.25 v, v pp = 12.5 v ?.3 v, v ss = 0.0 v, t a = 25? ??) test item symbol min typ max unit conditions input high- ea 14 to ea 0 , oe , ce v ih 2.4 v cc + 0.3 v level voltage input low- ea 14 to ea 0 , oe , ce v il ?.3 0.8 v level voltage output high- eo 7 to eo 0 v oh 2.4 v i oh = ?00 ? level voltage output low- eo 7 to eo 0 v ol 0.45 v i ol = 1.6 ma level voltage input leakage eo 7 to eo 0 , ea 14 to ea 0 ,|i li | 2 ? v in = current oe , ce 5.25 v/0.5 v v cc current i cc 40 ma v pp current i pp 40 ma table 4-5 ac characteristics (conditions: v cc = 6.0 v ?.25 v, v pp = 12.5 v ?.3 v, v ss = 0.0 v, t a = 25? ??) item symbol min typ max unit test conditions address setup time t as 2 s figure 4-5 * oe setup time t oes 2 s data setup time t ds 2 s address hold time t ah 0 s data hold time t dh 2 s data output disable time t df 0 130 ns v pp setup time t vps 2 s programming pulse width t pw 0.95 1.0 1.05 ms ce pulse width for overwrite t opw 2.85 78.75 ms programming v cc setup time t vcs 2 s data output delay time t oe 0 500 ns notes: * input pulse level: 0.8 to 2.2 v input rise time/fall time 20 ns timing reference levels input: 1.0 v, 2.0 v output: 0.8 v, 2.0 v 93 figure 4-5 prom write/verify timing 4.3.2 programming precautions 1. use the specified programming voltage and timing. the programming voltage in prom mode (v pp ) is 12.5 v. use of a higher voltage can permanently damage the chip. be especially careful with respect to prom programmer overshoot. setting the prom programmer to hitachi specifications for the hn27c256h or to intel specifications will result in a correct v pp of 12.5 v. 2. make sure the index marks on the prom programmer socket, socket adapter, and chip are properly aligned. if they are not, the chip may be destroyed by excessive current flow. before programming, be sure the chip is properly mounted in the prom programmer. address data v pp v cc ce oe v pp v cc input data write verify output data t as t ds t vps t vcs t pw t opw t oes t oe t dh t ah t df v gnd cc 94 3. avoid touching the socket adapter or chip during programming, since this may cause contact faults and write errors. 4. some commercially available eprom programmers execute a device test before writing, reading, or verifying. the device test is a leakage test of the eprom pins or ztat microcontroller pins. (a ztat microcontroller is a microcontroller with on-chip eprom.) the function of this test is to check whether the device is correctly inserted in the socket, by confirming that leakage current flow is above a certain minimum level. in devices like the h8/3714 in which the on-chip eprom is assigned to high-voltage pins (pmos open-drain pins), no leakage current flows in the sink direction. that may cause the device test to fail and prevent writing, reading, or verifying. if this occurs, switch the device test off. note that in some eprom programmers, the device test cannot be switched off. 95 4.3.3 reliability of written data an effective way to assure the data holding characteristics of the programmed chips is to bake them at 150?c, then screen them for data errors. this procedure quickly eliminates chips with prom memory cells prone to early data retention failure. figure 4-8 shows a flow chart of this screening procedure. figure 4-6 recommended screening procedure if write errors occur repeatedly while the same prom programmer is being used, stop programming and check for problems in the prom programmer and socket adapter, etc. please notify your hitachi representative of any problems occurring during programming or in screening after high-temperature baking. install write program and verify written data bake chips with power off 150 c ?10 c, 48 hr read and check program v = 4.5 v and 5.5 v note: * baking time is measured from when the oven reaches 150?. +8 hr ? hr cc * 96 section 5 ram 5.1 overview the h8/3714 has 512 bytes of high-speed static ram on-chip. the h8/3713 and the h8/3712 each has 384 bytes. the ram is connected to the cpu by a 16-bit data bus, allowing high-speed two-state access for both byte data and word data. 5.1.1 block diagram figure 5-1 shows a block diagram of the on-chip ram. figure 5-1 ram block diagram (h8/3714) 5.1.2 display ram area in the h8/3714, h8/3713 and h8/3712, ram addresses h'fec0 to h'feff are also used as a display ram for the vfd controller/driver. if the vfd controller/driver is not used, this area is available as an ordinary ram. internal data bus (upper 8 bits) even-numbered addresses odd-numbered addresses h'ff7e h'ff7f internal data bus (lower 8 bits) h'fd80 h'fd82 h'fd81 h'fd83 h'ff7e h'fd80 h'fd82 97 98 section 6 clock pulse generators 6.1 overview clock oscillator circuitry (cpg: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. the system clock pulse generator consists of a system clock oscillator, system clock divider, and a clock divider (prescaler s) for the on-chip peripheral modules. the subclock pulse generator consists of a subclock oscillator circuit, subclock divider, and a further subclock divider (prescaler w) for time-base use. 6.1.1 block diagram figure 6-1 shows a block diagram of the clock pulse generators. figure 6-1 block diagram of clock pulse generators /2 to /8192 system clock pulse generator system clock oscillator system clock divider (1/2) subclock oscillator subclock divider (1/8) prescaler s prescaler w subclock pulse generator ff f sub f /32 sub f osc 1 osc 2 x 1 x 2 f x f osc 99 6.2 system clock generator clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic oscillator, or by providing external clock input. 1. connecting a crystal oscillator circuit configuration figure 6-2 shows a typical method of connecting a crystal oscillator. figure 6-2 typical connection to crystal oscillator crystal oscillator figure 6-3 shows the equivalent circuit of the crystal oscillator. an oscillator having the characteristics given in table 6-1 should be used. figure 6-3 equivalent circuit of crystal oscillator table 6-1 crystal oscillator parameters frequency (mhz) 24 8 r s max ( ) 500 100 50 c o max (pf) 7 7 7 1 2 c 1 c 2 osc osc r f r f = 1 m w ?0% c 1 = c = 12 pf ?0% 2 c l c 0 lr s osc 1 osc 2 100 2. connecting a ceramic oscillator circuit configuration figure 6-4 shows a typical method of connecting a ceramic oscillator. figure 6-4 typical connection to ceramic oscillator 3. notes on board design when generating clock pulses by connecting a crystal or ceramic oscillator, pay careful attention to the following points. avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely affected by induction currents. (see figure 6-5.) the board should be designed so that the oscillator and load capacitors are located as close as possible to pins osc 1 and osc 2 . osc osc c 1 c 2 2 1 r f ceramic oscillator r f : c 1 : c 2 : 1 m w ?0% 30 pf ?0% 30 pf ?0% 101 figure 6-5 board design of oscillator circuit 4. external clock input circuit configuration when an external clock is used, it is input at pin osc 1 . pin osc 2 should be left open. figure 6-6 shows a typical connection. figure 6-6 external clock input (example) external clock frequency twice clock frequency ( f ) duty cycle 45% to 55% osc osc c 2 c 1 signal a h8/3714 series microcontroller signal b 2 1 to be avoided osc osc open external clock input 1 2 102 6.3 subclock generator 1. connecting a 32.768 khz crystal oscillator clock pulses can be supplied to the subclock divider by connecting a 32.768 khz crystal oscillator, as shown in figure 6-7. follow the same precautions as noted for the system clock. figure 6-7 typical connection to crystal oscillator (subclock) figure 6-8 shows the equivalent circuit of the crystal oscillator. figure 6-8 equivalent circuit of crystal oscillator 2. pin connection when not using subclock when the subclock is not used, connect v cc to pin x 1 and leave pin x 2 open, as shown in figure 6-9. x x c 1 c 2 1 2 c 1 = c 2 = 15 pf typ c s c 0 l r s c 0 = 1.5 pf typ r s = 14 k typ f = 32.768 khz w 103 figure 6-9 pin connection when not using subclock x x 1 2 v cc open 104 section 7 i/o ports 7.1 overview the h8/3714 series has five 8-bit i/o ports (of which four are high-voltage ports), one 6-bit i/o port*, and one 8-bit input port. table 7-1 indicates the functions of each port. ports 1 and 9 are standard input/output ports, consisting of a port control register (pcr) that controls input and output, and a port data register (pdr) for storing output data. input or output can be assigned to individual bits. ports 4, 5, 6, and 7 are high-voltage ports, able to handle an applied voltage of v cc ?40 v. input and output are controlled for individual bits by reading from and writing to pdr. note: * pin p1 7 of port 1 is a high-voltage input-only pin, while pin p1 6 is a standard input-only pin. pins p1 2 and p1 3 are not present. reading a port gives the following results. reading a standard port reading a pin assigned to general-purpose input (pcr = 0) gives the pin level. reading a pin assigned to general-purpose output (pcr = 1) gives the value of the corresponding pdr bit. reading a pin assigned to an on-chip peripheral function gives the pin level. reading a high-voltage port reading a pin assigned to general-purpose input/output gives the pin level. reading a pin assigned to digit output or segment output use gives the value of the corresponding pdr bit. 105 table 1 port functions function switching port description pins other functions register port 0 8-bit standard input port p0 7 to p0 0 / analog data input channels pmr0 an 7 to an 0 7 to 0 port 1 pin p1 7 : 1-bit high-voltage p1 7 /v disp power supply for vfd driver mask input port option pin p1 6 : 1-bit standard input p1 6 / event timer d event input pmr1 port pins p1 5 , p1 4 , p1 1 , and p1 0 :p1 5 /irq 5 / external interrupt 5; pmr1 4-bit standard i/o port tmoe timer e output pmr4 p1 4 /irq 4 external interrupts 4, 1, and 0 pmr1 p1 1 /irq 1 p1 0 /irq 0 port 4 8-bit high-voltage i/o port p4 7 to p4 0 / vfd segment pins 23 to 16 vfsr fs 23 to fs 16 port 5 8-bit high-voltage i/o port p5 7 to p5 0 / vfd segment pins 15 to 8 vfsr fs 15 to fs 8 port 6 8-bit high-voltage i/o port p6 7 to p6 0 / vfd digit pins 7 to 0/segment dbr fd 7 to fd 0 / pins 0 to 7 vfsr fs 0 to fs 7 vfdr port 7 8-bit high-voltage i/o port p7 7 to p7 0 / vfd digit pins 15 to 8 vfdr fd 15 to fd 8 port 9 8-bit standard i/o port p9 7 /ud timer c count-up/down pmr2 selection pmr3 p9 6 /so 2 serial communication interface 2 data output p9 5 /si 2 / cs serial communication interface 2 data input/chip select output p9 4 /sck 2 serial communication interface 2 clock i/o p9 3 /so 1 serial communication interface 1 data output p9 2 /si 1 serial communication interface 1 data input p9 1 /sck 1 serial communication interface 1 clock i/o p9 0 /pwm 14-bit pwm waveform output pin note: pins p1 2 and p1 3 , and ports p2, p3, and p8 are not included in these versions. 106 7.1.1 port types and mask options the choice of i/o pin options and the resulting states are shown in table 7-2. upon reset, the pdr, pcr, and pmr registers are initialized, cancelling the choices of peripheral functions. when the chip goes to a low-power mode, the on-chip peripheral function input gates are always on, so unless input levels are fixed there will be an increase in dissipated current. table 7-2 choice of i/o port options for standard i/o pins class pins with mos pull-up (type b) no mos pull-up (type c) i/o pins p1 5 , p1 4 , with mos pull-up no mos pull-up p1 1 , p1 0 , p9 7 to p9 0 input-only pins p1 6 with mos pull-up no mos pull-up on-chip peripheral sck 2 , sck 1 with mos pull-up no mos pull-up function i/o pins (output mode) * on-chip peripheral so 2 , so 1 , with mos pull-up no mos pull-up function output pins pwm, tmoe on-chip peripheral sck 2 , sck 1 with mos pull-up no mos pull-up function input pins (input mode) * si 2 , si 1 , irq 5 , irq 4 , irq 1 , irq 0 ud, event note: if external clock input mode is selected when the serial communication interface is used, pins sck 2 and sck 1 will be input-only pins. for high-voltage pins class pins no mos pull-down (type d) with mos pull-down (type e) i/o pins p4 7 to p4 0 , no mos pull-down with mos pull-down. p5 7 to p5 0 , source of pull-down transistor p6 7 to p6 0 , connected to v disp power p7 7 to p7 0 supply. input-only pins p1 7 no mos pull-down connected to v disp power supply. on-chip peripheral fs 23 to fs 0 , no mos pull-down with mos pull-down. function output pins fd 15 to fd 0 source of pull-down transistor connected to v disp power supply. 107 table 7-3 shows the mask options with mask rom versions. a mask rom version is compatible with a ztat version only when c and d options are selected for all pins. table 7-3 correspondence between mask rom and ztat versions type bcde mask rom option option option option z tat ? fixed fixed notes 1. when circuit type e, ?ith mos pull-down,?is chosen, the source of the mos pull-down is connected to the v disp power supply. accordingly, the mask option making pin p1 7 /v disp a v disp power supply pin must also be chosen. 2. type c, ?o mos pull-up, is the only option available for port 0. 7.1.2 mos pull-up ports 1* and 9, which are standard input/output ports, can be designated by mask options as having or not having mos pull-up transistors for their (cmos) outputs. (this does not apply to ztat versions.) figure 7-1 shows the mos pull-up circuit configuration. when ?ith mos pull-up?is selected by mask option, the mos pull-up will normally be on, regardless of the port data register (pdr) and port control register (pcr) settings. (see table 7-4.) note: * pin p1 7 /v disp is a high-voltage pin, so the mos pull-up option cannot be selected for this pin. 108 figure 7-1 mos pull-up circuit configuration table 7-4 mos pull-up control mask option with mos pull-up (type b) no mos pull-up (type c) pcr 0 1 0 1 pdr 01 01 01 01 cmos buffer pmos off off off on off off off on nmos off off on off off off on off mos pull-up on on on on v cc v ss cmos buffer v cc pdr pcr input data mos pull-up stby * 2 * 1 notes: 1. 2. dotted lines indicate mask option. in low-power modes (except sleep mode), the mos pull-up is switched off by a stby signal. 109 7.1.3 mos pull-down ports 4, 5, 6, and 7, which are high-voltage i/o ports, can be designated by mask option as having or not having mos pull-down resistors for their (pmos open-drain) outputs. (this does not apply to ztat versions.) figure 7-2 shows the mos pull-down circuit configuration. when the ?ith mos pull-down?option is chosen, the source of the mos pull-down is connected to the v disp power supply. accordingly, the mask option making pin p1 7 /v disp a v disp power supply pin must also be chosen. figure 7-2 mos pull-down circuit configuration v cc v disp pdr input data stby * input control note: * dotted lines indicate mask option. 110 7.2 port 0 7.2.1 overview port 0 is an 8-bit standard input-only port. figure 7-3 shows the pin configuration. figure 7-3 port 0 pin configuration 7.2.2 register configuration and description table 7-5 shows the port 0 register configuration. table 7-5 port 0 registers name abbrev. r/w initial value address port mode register 0 pmr0 w h'00 h'ffef port data register 0 pdr0 r h'ffd0 1. port mode register 0 (pmr0) each pmr0 bit designates whether the corresponding port 0 pin is to be used for general input or as an analog input channel to the a/d converter. upon reset, pmr0 is initialized to h'00. p0 /an (input) p0 /an (input) p0 /an (input) p0 /an (input) p0 /an (input) p0 /an (input) p0 /an (input) p0 /an (input) 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 port 0 bit initial value read/write 7 an7 0 w 6 an6 0 w 5 an5 0 w 4 an4 0 w 3 an3 0 w 0 an0 0 w 2 an2 0 w 1 an1 0 w 111 bit n ann explanation 0 pin p0 n /an n is used for general input. (initial value) 1 pin p0 n /an n is an analog input channel. (n = 0 to 7) 2. port data register 0 (pdr0) when the corresponding bit in pmr0 is 0, the pin state can be read from pdr0. if the corresponding pmr0 bit is 1, pdr0 is read as 1. 7.2.3 pin functions table 7-6 gives the port 0 pin functions. table 7-6 port 0 pin functions pin pin functions and selection method p0 7 /an 7 to p0 0 /an 0 functions are switched as follows by means of bits an 7 to an 0 in pmr0. an n 01 pin function p0 n input pin an n input pin 7.2.4 pin states table 7-7 shows the port 0 pin states in each operating mode. table 7-7 port 0 pin states pins reset sleep standby watch subactive active p0 7 /an 7 to high previous high high high normal p0 0 /an 0 impedance state impedance impedance impedance operation retained bit initial value read/write 7 pdr0 r 6 pdr0 r 5 pdr0 r 4 pdr0 r 3 pdr0 r 0 pdr0 r 2 pdr0 r 1 pdr0 r 7 65432 10 112 7.3 port 1 7.3.1 overview port 1 consists of four standard i/o pins, one standard input-only pin, and one high-voltage input- only pin. figure 7-4 shows the pin configuration. figure 7-4 port 1 pin configuration 7.3.2 register configuration and description table 7-8 shows the port 1 register configuration. table 7-8 port 1 registers name abbrev. r/w initial value address port mode register 1 pmr1 r/w h'0c h'ffeb port control register 1 pcr1 w h'cc h'ffe1 port data register 1 pdr1 r/w not fixed h'ffd1 port mode register 4 pmr4 r/w h'0f h'ffee 1. port mode register 1 (pmr1) p1 /v p1 /event p1 /irq /tmoe p1 /irq p1 /irq p1 /irq 7 6 5 4 1 0 disp port 1 5 4 1 0 (high-voltage input or power supply) (input/input) (io/input/output) (io/input) (io/input) (io/input) note: io indicates input/output. bit initial value read/write 7 0 r/w 6 event 0 r/w 5 irqc5 0 r/w 4 irqc4 0 r/w 3 1 0 irqc0 0 r/w 2 1 1 irqc1 0 r/w noise cancel 113 pmr1 is an 8-bit read/write register that controls the selection of pin functions for pins p1 6 / event , p1 5 /irq 5 , p1 4 /irq 4 , p1 1 /irq 1 , and p1 0 /irq 0 , and turns the irq 0 noise cancellation function on and off. upon reset, pmr1 is initialized to h'0c. note: before switching pin functions using bits irq5 to irq0 in pmr1, first disable the corresponding interrupts by clearing their interrupt enable bits. after the pin functions have been switched, issue any instruction, then clear the interrupt request flags to 0. for details see section 3.2.3 1, port mode register (pmr1). bit 7: noise cancel (noise cancel) this bit turns the irq 0 noise canceller function on and off. in standby, watch, and subactive modes the noise canceller function is off regardless of the setting of this bit. bit 7 noise cancel explanation 0 noise canceller function is off. (initial value) 1 noise canceller function is on. input is sampled at intervals of 256 states. if two consecutive input values do not match, noise is assumed. bit 6: p1 6 / event pin function switch (event) this bit selects whether pin p1 6 / event is used as p1 6 or as event . bit 6 event explanation 0p1 6 /event pin functions as p1 6 . * (initial value) 1p1 6 /event pin functions as event (timer d event input). note: * even when pin p1 6 /event is used as p1 6 , the timer d counter may increment when pin p1 6 is read. if timer d is used the counter must be cleared by means of the clr bit in timer mode register d (tmd). bit 5: p1 5 /irq 5 /tmoe pin function switch (irqc5) this bit selects whether pin p1 5 /irq 5 /tmoe is used as p1 5 / tmoe or as irq 5 . bit 5 irqc5 explanation 0p1 5 /irq 5 /tmoe pin functions as p1 5 /tmoe. (initial value) 1p1 5 /irq 5 /tmoe pin functions for irq 5 input. 114 bit 4: p1 4 /irq 4 pin function switch (irqc4) this bit selects whether pin p1 4 /irq 4 is used as p1 4 or as irq 4 . bit 4 irqc4 explanation 0p1 4 /irq 4 pin functions as p1 4 . (initial value) 1p1 4 /irq 4 pin functions for irq 4 * input. note: * rising or falling edge sensing can be designated for pin irq 4 . for details see 3.2.3 (2), irq edge select register (iegr). bits 3 and 2: reserved bits bits 3 and 2 are reserved; they always read 1, and cannot be modified. bit 1: p1 1 /irq 1 pin function switch (irqc1) this bit selects whether pin p1 1 /irq 1 is used as p1 1 or as irq 1 . bit 1 irqc1 explanation 0p1 1 /irq 1 pin functions as p1 1 . (initial value) 1p1 1 /irq 1 pin functions for irq 1 * input. note: * rising or falling edge sensing can be designated for pin irq 1 . for details see 3.2.3 (2), irq edge select register (iegr). bit 0: p1 0 /irq 0 pin function switch (irqc0) this bit selects whether pin p1 0 /irq 0 is used as p1 0 or as irq 0 . bit 0 irqc0 explanation 0p1 0 /irq 0 pin functions as p1 0 . (initial value) 1p1 0 /irq 0 pin functions for irq 0 * input. note: * rising or falling edge sensing can be designated for pin irq 0 . for details see 3.2.3 (2), irq edge select register (iegr). 115 2. port control register 1 (pcr1) pcr1 is an 8-bit register for controlling whether each of port 1 pins p1 5 , p1 4 , p1 1 , and p1 0 functions as an input pin or output pin. setting a pcr1 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. bits 7, 6, 3, and 2 are reserved bits that cannot be modified and always read 1. the settings in pcr1 and in pdr1 are valid when the affected pin is designated in pmr1 as a general i/o pin. upon reset, pcr1 is initialized to h'cc. 3. port data register 1 (pdr1) note: * pins p1 7 and p1 6 are for input only; reading pdr1 always gives the level of these pins. pdr1 is an 8-bit register that stores data for pins p1 5 , p1 4 , p1 1 , and p1 0 . if port 1 is read while pcr1 bits are set to 1, the values stored in pdr1 are read, regardless of the actual pin states. if port 1 is read while pcr1 bits are cleared to 0, the pin states are read. bits 3 and 2 are reserved bits that cannot be modified and always read 1. bit initial value read/write 7 1 6 1 5 pcr1 0 w 4 pcr1 0 w 3 1 0 pcr1 0 w 2 1 1 pcr1 0 w 54 10 bit initial value read/write 7 6 5 pdr1 0 r/w 4 pdr1 0 r/w 3 1 0 pdr1 0 r/w 2 1 1 pdr1 0 r/w 54 10 ** 116 4. port mode register 4 (pmr4) pmr4 is an 8-bit read/write register that switches the p1 5 /irq 5 /tmoe pin function and controls tmoe pin waveform output. bits 3 to 0 are reserved; they always read 1, and cannot be modified. upon reset, pmr4 is initialized to h'0f. bit 7: timer e output select (teo) bit 6: timer e output on/off (teo on) bit 5: fixed frequency select (freq) bit 4: variable frequency select (vrfr) p1 5 /irq 5 /tmoe pin functions are switched as follows, by means of bits 7 to 4 of pmr4 and bit irqc5 of pmr1. pmr1 pmr4 description bit 5 bit 7 bit 6 bit 5 bit 4 irqc5 teo teo on freq vrfr pin function pin state 000 00p1 5 pin standard i/o port (initial value) 00 *** p1 5 pin standard i/o port 010 ** tmoe output pin (off) low level output 0 1 1 0 0 tmoe output pin (on) fixed frequency output: ( f /2048) 1.95 khz ( f = 4 mhz) 0.98 khz ( f = 2 mhz) 0 1 1 1 0 tmoe output pin (on) fixed frequency output: ( f /1024) 3.9 khz ( f = 4 mhz) 1.95 khz ( f = 2 mhz) 011 * 1 tmoe output pin (on) variable frequency output: toggled by timer e overflow 1 ** * * irq 5 input pin external interrupt input note: * don? care bit initial value read/write 7 teo 0 r/w 6 teo on 0 r/w 5 freq 0 r/w 4 vrfr 0 r/w 3 1 0 1 2 1 1 1 117 7.3.3 pin functions table 7-9 shows the port 1 pin functions. table 7-9 port 1 pin functions pin pin functions and selection method p1 7 /v disp selected by mask option p1 7 high-voltage input pin power supply for vfd driving (v disp ) p1 6 / event function is switched as follows by event bit in pmr1 event 0 1 pin function p1 6 input pin event input pin * note: timer d event input function is switched as follows by bits irqc5, irqc4, irqc1, and irqc0 * in pmr1 and bit n in pcr1 pmr1 0 1 pcr1 n 01 pin function p1 n input pin p1 n output pin irq n input pin notes: 1. before switching pin functions using bits irqc5, irqc4, irqc1, and irqc0 in pmr1, first disable the corresponding interrupts by clearing their interrupt enable bits. after the pin functions have been switched, issue any instruction, then clear the interrupt request flags to 0. for details see section 3.2.3 (1), port mode register (pmr1). 2. before entering power-down mode, pins set to external interrupt input by bits irqc5, irqc4, irqc1, and irqc0 in pmr1, should be kept from floating by external connection, or should be switched to general i/o in pmr1 prior to the state transition. 3. for details on the tmoe function, refer to section 7.3.2 (4), port mode register 4 (pmr4). irq 4 , irq 1 , and irq 0 input can be set for either rising edge or falling edge detection by register iegr. for details, refer to section 3.2.3 (2), irq edge select register (iegr). irq 0 and irq 1 can be used as event input pins for timer b and timer c, respectively. for details, refer to section 8, timers. p1 5 /irq 5 /tmoe, p1 4 /irq 4 , p1 1 /irq 1 , p1 0 /irq 0 118 7.3.4 pin states table 7-10 shows the port 1 pin states in each operating mode. table 7-10 port 1 pin states pins reset sleep standby watch subactive active p1 7 /v disp high high high high high normal impedance impedance impedance impedance impedance operation or v disp or v disp or v disp or v disp or v disp or v disp p1 6 / event , high previous high high high normal p1 5 /irq 5 / impedance state impedance impedance impedance operation tmoe, or pulled up retained p1 4 /irq 4 , p1 1 /irq 1 , p1 0 /irq 0 119 7.4 port 4 7.4.1 overview port 4 is an 8-bit high-voltage i/o port. figure 7-5 shows the pin configuration. figure 7-5 port 4 pin configuration 7.4.2 register configuration and description table 7-11 shows the port 4 register configuration. table 7-11 port 4 registers name abbrev. r/w initial value address port data register 4 pdr4 r/w h'00 h'ffd4 1. port data register 4 (pdr4) pdr4 is an 8-bit register for storing the data of port 4 pins p4 7 to p4 0 . upon reset, pdr4 is initialized to h'00. p4 /fs p4 /fs p4 /fs p4 /fs p4 /fs p4 /fs p4 /fs p4 /fs 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 port 4 (io/output) (io/output) (io/output) (io/output) (io/output) (io/output) (io/output) (io/output) note: io indicates input/output. bit initial value read/write 7 pdr4 0 r/w 6 pdr4 0 r/w 5 pdr4 0 r/w 4 pdr4 0 r/w 3 pdr4 0 r/w 0 pdr4 0 r/w 2 pdr4 0 r/w 1 pdr4 0 r/w 3210 4 5 6 7 120 7.4.3 pin functions table 7-12 shows the port 4 pin functions. table 7-12 port 4 pin functions pin pin functions and selection method p4 7 /fs 23 to after designation of the segment pins to be used in bits sr4 to sr0 of the vfd p4 0 /fs 16 segment control register (vfsr), bit vfde in the digit beginning register (dbr) is set to 1 and vfd controller/driver operation is started. during key scan intervals, pins designated for segment output can be used by the cpu as general-purpose ports. even while the vfd controller/driver is operating, it is possible to switch segment pins to general-purpose ports by writing 0 in the vflag bit of vfsr. vflag 0 1 pin function pins p4 7 to p4 0 are all pins designated by bits general-purpose i/o pins. sr4 to sr0 are segment output pins. * other pins are for general i/o. note: * when a pin functioning as a segment output pin is read, the value of the corresponding bit in pdr4 is read. 7.4.4 pin states table 7-13 shows the port 4 pin states in each operating mode. table 7-13 port 4 pin states pins reset sleep standby watch subactive active p4 7 /fs 23 to high previous high high high normal p4 0 /fs 16 impedance or state impedance or impedance or impedance or operation pulled down retained pulled down pulled down pulled down 121 7.5 port 5 7.5.1 overview port 5 is an 8-bit high-voltage i/o port. figure 7-6 shows the pin configuration. figure 7-6 port 5 pin configuration 7.5.2 register configuration and description table 7-14 shows the port 5 register configuration. table 7-14 port 5 registers name abbrev. r/w initial value address port data register 5 pdr5 r/w h'00 h'ffd5 1. port data register 5 (pdr5) pdr5 is an 8-bit register for storing the data of port 5 pins p5 7 to p5 0 . upon reset, pdr5 is initialized to h'00. p5 /fs p5 /fs p5 /fs p5 /fs p5 /fs p5 /fs p5 /fs p5 /fs 7 6 5 4 3 2 1 0 8 9 10 11 12 13 14 15 port 5 (io/output) (io/output) (io/output) (io/output) (io/output) (io/output) (io/output) (io/output) note: io indicates input/output. bit initial value read/write 7 pdr5 0 r/w 6 pdr5 0 r/w 5 pdr5 0 r/w 4 pdr5 0 r/w 3 pdr5 0 r/w 0 pdr5 0 r/w 2 pdr5 0 r/w 1 pdr5 0 r/w 3210 4 5 6 7 122 7.5.3 pin functions table 7-15 shows the port 5 pin functions. table 7-15 port 5 pin functions pin pin functions and selection method p5 7 /fs 8 to after designation of the segment pins to be used in bits sr4 to sr0 of the vfd p5 0 /fs 15 segment control register (vfsr), bit vfde in the digit beginning register (dbr) is set to 1 and vfd controller/driver operation is started. during key scan intervals, pins designated for segment output can be used by the cpu as general-purpose ports. even while the vfd controller/driver is operating, it is possible to switch segment pins to general-purpose ports by writing 0 in the vflag bit of vfsr. vflag 0 1 pin function pins p5 7 to p5 0 are all pins designated by bits general-purpose i/o pins. sr4 to sr0 are segment output pins. * other pins are for general i/o. note: * when a pin functioning as a segment output pin is read, the value of the corresponding bit in pdr5 is read. 7.5.4 pin states table 7-16 shows the port 5 pin states in each operating mode. table 7-16 port 5 pin states pins reset sleep standby watch subactive active p5 7 /fs 8 to high previous high high high normal p5 0 /fs 15 impedance or state impedance or impedance or impedance or operation pulled down retained pulled down pulled down pulled down 123 7.6 port 6 7.6.1 overview port 6 is an 8-bit high-voltage i/o port. figure 7-7 shows the pin configuration. figure 7-7 port 6 pin configuration 7.6.2 register configuration and description table 7-17 shows the port 6 register configuration. table 7-17 port 6 registers name abbrev. r/w initial value address port data register 6 pdr6 r/w h'00 h'ffd6 1. port data register 6 (pdr6) pdr6 is an 8-bit register for storing the data of port 6 pins p6 7 to p6 0 . upon reset, pdr6 is initialized to h'00. p6 /fd /fs p6 /fd /fs p6 /fd /fs p6 /fd /fs p6 /fd /fs p6 /fd /fs p6 /fd /fs p6 /fd /fs 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 port 6 0 1 2 3 4 5 6 7 (io/output/output) (io/output/output) (io/output/output) (io/output/output) (io/output/output) (io/output/output) (io/output/output) (io/output/output) note: io indicates input/output. bit initial value read/write 7 pdr6 0 r/w 6 pdr6 0 r/w 5 pdr6 0 r/w 4 pdr6 0 r/w 3 pdr6 0 r/w 0 pdr6 0 r/w 2 pdr6 0 r/w 1 pdr6 0 r/w 3210 4 5 6 7 124 7.6.3 pin functions table 7-18 shows the port 6 pin functions. table 7-18 port 6 pin functions pin pin functions and selection method p6 7 /fd 7 /fs 0 to after designation of the digit pins and segment pins to be used in bits dr3 to p6 0 /fd 0 /fs 7 dr0 of the vfd digit control register (vfdr), bits sr4 to sr0 of the vfd segment control register (vfsr), and bits dbr3 to dbr0 of the digit beginning register (dbr), bit vfde in dbr is set to 1 and vfd controller/driver operation is started. during key scan intervals, pins designated for digit or segment output can be used by the cpu as general-purpose ports. even while the vfd controller/driver is operating, it is possible to switch digit pins or segment pins to general-purpose ports by writing 0 in the vflag bit of vfsr. vflag 0 1 pin function pins p6 7 to p6 0 are all pins are designated as digit general-purpose i/o pins. output pins, * segment output pins, * or general i/o pins by bits dr3 to dr0, sr4 to sr0, and dbr3 to dbr0. note: * when a pin functioning as a digit output pin or segment output pin is read, the value of the corresponding bit in pdr6 is read. 7.6.4 pin states table 7-19 shows the port 6 pin states in each operating mode. table 7-19 port 6 pin states pins reset sleep standby watch subactive active p6 7 /fd 7 / high previous high high high normal fs 0 to impedance or state impedance or impedance or impedance or operation p6 0 /fd 0 / pulled down retained pulled down pulled down pulled down fs 7 125 7.7 port 7 7.7.1 overview port 7 is an 8-bit high-voltage i/o port. figure 7-8 shows the pin configuration. figure 7-8 port 7 pin configuration 7.7.2 register configuration and description table 7-20 shows the port 7 register configuration. table 7-20 port 7 registers name abbrev. r/w initial value address port data register 7 pdr7 r/w h'00 h'ffd7 1. port data register 7 (pdr7) pdr7 is an 8-bit register for storing the data of port 7 pins p7 7 to p7 0 . upon reset, pdr7 is initialized to h'00. p7 /fd p7 /fd p7 /fd p7 /fd p7 /fd p7 /fd p7 /fd p7 /fd 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 port 7 (io/output) (io/output) (io/output) (io/output) (io/output) (io/output) (io/output) (io/output) note: io indicates input/output. bit initial value read/write 7 pdr7 0 r/w 6 pdr7 0 r/w 5 pdr7 0 r/w 4 pdr7 0 r/w 3 pdr7 0 r/w 0 pdr7 0 r/w 2 pdr7 0 r/w 1 pdr7 0 r/w 3210 4 5 6 7 126 7.7.3 pin functions table 7-21 shows the port 7 pin functions. table 7-21 port 7 pin functions pin pin functions and selection method p7 7 /fd 15 to after designation of the digit pins to be used, in bits dr3 to dr0 of the vfd p7 0 /fd 8 digit control register (vfdr), bit vfde in the digit beginning register (dbr) is set to 1 and vfd controller/driver operation is started. even while the vfd controller/driver is operating, it is possible to switch digit pins to general- purpose ports by writing 0 in the vflag bit of vfsr. vflag 0 1 pin function pins p7 7 to p7 0 are all pins designated by bits general-purpose i/o pins. dr3 to dr0 are digit output pins. * other pins are for general i/o. note: * when a pin functioning as a digit output pin is read, the value of the corresponding bit in pdr7 is read. 7.7.4 pin states table 7-22 shows the port 7 pin states in each operating mode. table 7-22 port 7 pin states pins reset sleep standby watch subactive active p7 7 /fd 15 to high previous high high high normal p7 0 /fd 8 impedance or state impedance or impedance or impedance or operation pulled down retained pulled down pulled down pulled down 127 7.8 port 9 7.8.1 overview port 9 is an 8-bit standard i/o port. figure 7-9 shows the pin configuration. figure 7-9 port 9 pin configuration 7.8.2 register configuration and description table 7-23 shows the port 9 register configuration. table 7-23 port 9 registers name abbrev. r/w initial value address port mode register 2 pmr2 r/w h'00 h'ffec port control register 9 pcr9 w h'00 h'ffe9 port data register 9 pdr9 r/w h'00 h'ffd9 1. port mode register 2 (pmr2) pmr2 is an 8-bit read/write register, controlling the selection of port 9 pin functions. upon reset, pmr2 is initialized to h'00. p9 /ud p9 /so p9 /si /cs p9 /sck p9 /so p9 /si p9 /sck p9 /pwm 7 6 5 4 3 2 1 0 port 9 2 2 2 1 1 1 (io/input) (io/output) (io/input/output) (io/io) (io/output) (io/input) (io/io) (io/output) note: io indicates input/output. bit initial value read/write 7 0 r/w 6 so2 0 r/w 5 si2 0 r/w 4 sck2 0 r/w 3 so1 0 r/w 0 pwm 0 r/w 2 si1 0 r/w 1 sck1 0 r/w up/ down 128 bit 7: p9 7 /ud pin function switch (up/down) this bit selects whether pin p9 7 /ud is used for general-purpose i/o or for timer c up/down control input. up/down control input (ud) is valid only when bit tmc6 = 1 in timer mode register c (tmc). bit 7 up/down description 0p9 7 /ud pin functions for p9 7 input/output. (initial value) 1p9 7 /ud pin functions for ud input. if bit tmc6 in tmc is set to 1, then when the ud input is high, timer c counts down, and when ud is low, timer c counts up. bit 6: p9 6 /so 2 pin function switch (so2) this bit selects whether pin p9 6 /so 2 functions as the p9 6 i/o pin or the so 2 output pin. bit 6 so2 description 0p9 6 /so 2 pin functions for p9 6 input/output. (initial value) 1p9 6 /so 2 pin functions for so 2 output. bit 5: p9 5 /si 2 / cs pin function switch (si2) this bit selects whether pin p9 5 /si 2 / cs functions as the p9 5 i/o pin or the si 2 input/ cs output pin. for the switching between si 2 input and cs output see 11.2.5, port mode register 3 (pmr3). bit 5 si2 description 0p9 5 /si 2 /cs pin functions for p9 5 input/output. (initial value) 1p9 5 /si 2 /cs pin functions for si 2 input or cs output. bit 4: p9 4 /sck 2 pin function switch (sck2) this bit selects whether pin p9 4 /sck 2 functions as the p9 4 i/o pin or the sck 2 i/o pin. bit 4 sck2 description 0p9 4 /sck 2 pin functions for p9 4 input/output. (initial value) 1p9 4 /sck 2 pin functions for sck 2 input/output. the clock input/output direction and the divider ratio are set in serial mode register 2 (smr2). 129 bit 3: p9 3 /so 1 pin function switch (so1) this bit selects whether pin p9 3 /so 1 functions as the p9 3 i/o pin or the so 1 output pin. bit 3 so1 description 0p9 3 /so 1 pin functions for p9 3 input/output. (initial value) 1p9 3 /so 1 pin functions for so 1 output. bit 2: p9 2 /si 1 pin function switch (si1) this bit selects whether pin p9 2 /si 1 functions as the p9 2 i/o pin or the si 1 input pin. bit 2 si1 description 0p9 2 /si 1 pin functions for p9 2 input/output. (initial value) 1p9 2 /si 1 pin functions for si 1 input. bit 1: p9 1 /sck 1 pin function switch (sck1) this bit selects whether pin p9 1 /sck 1 functions as the p9 4 i/o pin or the sck 1 i/o pin. bit 1 sck1 description 0p9 1 /sck 1 pin functions for p9 1 input/output. (initial value) 1p9 1 /sck 1 pin functions for sck 1 input/output. the clock input/output direction and the divider ratio are set in serial mode register 1 (smr1). bit 0: p9 0 /pwm pin function switch (pwm) this bit selects whether pin p9 0 /pwm pin functions as the p9 0 i/o pin or the pwm output pin. bit 0 pwm description 0p9 0 /pwm pin functions for p9 0 input/output. (initial value) 1p9 0 /pwm pin functions for pwm output. 130 2. port control register 9 (pcr9) pcr9 is an 8-bit register for controlling whether each of port 9 pins p9 7 to p9 0 functions as an input or output pin. setting a pcr9 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr9 and pdr9 are valid when the affected pin is designated in pmr2 as a general-purpose i/o pin. pcr9 is a write-only register, which always reads as all 1. upon reset, pcr9 is initialized to h'00. 3. port data register 9 (pdr9) pdr9 is an 8-bit register that stores data for port 9 pins p9 7 to p9 0 . if port 9 is read while pcr9 bits are set to 1, the values stored in pdr9 are read, regardless of the actual pin states. if port 9 is read while pcr9 bits are cleared to 0, the pin states are read. upon reset, pdr9 is initialized to h'00. bit initial value read/write 7 pcr9 0 w 6 pcr9 0 w 5 pcr9 0 w 4 pcr9 0 w 3 pcr9 0 w 0 pcr9 0 w 2 pcr9 0 w 1 pcr9 0 w 5432 10 6 7 bit initial value read/write 7 pdr9 0 r/w 6 pdr9 0 r/w 5 pdr9 0 r/w 4 pdr9 0 r/w 3 pdr9 0 r/w 0 pdr9 0 r/w 2 pdr9 0 r/w 1 pdr9 0 r/w 3210 4 5 6 7 131 7.8.3 pin functions table 7-24 shows the port 9 pin functions. table 7-24 port 9 pin functions pin pin functions and selection method p9 7 /ud functions are switched as follows by means of the up/down bit * in pmr2 and bit pcr9 7 in pcr9. up/down 0 1 pcr9 7 01 pin function p9 7 input pin p9 7 output pin ud input pin note: * before entering power-down mode, if this pin is set to ud input by the up/down bit in pmr2, it should be kept from floating by external connection or should be set to general i/o use by clearing the up/down bit to 0 prior to the state transition. p9 6 /so 2 * functions are switched as follows by means of bit so2 in pmr2 and bit pcr9 6 in pcr9. so2 0 1 pcr9 6 01 pin function p9 6 input pin p9 6 output pin so 2 output pin note: * the pmos buffer transistor of pin p9 6 /so 2 can be enabled or disabled by the so2pmos bit in pmr3. for details see 11.2.5, port mode register 3 (pmr3). p9 5 /si 2 / functions are switched as follows by means of bit si2 in pmr2, * bit cs in cs pmr3, and bit pcr9 5 in pcr9. si2 0 1 cs 0 1 pcr9 5 01 pin function p9 5 input pin p9 5 output pin si 2 input pin cs output pin note: * before entering power-down mode, if this pin is set to si 2 input by bit si2 in pmr2, it should be kept from floating by external connection or should be set to general i/o use by clearing bit si2 to 0 prior to the state transition. 132 table 7-24 port 9 pin functions (cont) pin pin functions and selection method p9 4 /sck 2 functions are switched as follows by means of bit sck2 * in pmr2, bits ps1 and ps0 * in serial control register 2 (scr2), and bit pcr9 4 in pcr9. sck2 0 1 ps1, 0 not 11 11 pcr9 4 01 pin function p9 4 input pin p9 4 output pin sck 2 output pin sck 2 input pin note: * before entering power-down mode, if this pin is set to sck 2 input by bit sck2 in pmr2 and bits ps1 and ps0 in scr2, it should be kept from floating by external connection, or else should be set to some other use by changing bits sck2 and bits ps1 and ps0 prior to the state transition. for the settings of bits ps1 and ps0 in scr2, see 11.2.3, serial control register 2 (scr2). p9 3 /so 1 * functions are switched as follows by means of bit so1 in pmr2 and bit pcr9 3 in pcr9. so1 0 1 pcr9 3 01 pin function p9 3 input pin p9 3 output pin so 1 output pin note: * the pmos buffer transistor of pin p9 3 /so 1 can be enabled or disabled by the so1pmos bit in pmr3. for details see 10.2.6, port mode register 3 (pmr3). p9 2 /si 1 functions are switched as follows by means of bit si1 * in pmr2 and bit pcr9 2 in pcr9. si1 0 1 pcr9 2 01 pin function p9 2 input pin p9 2 output pin si 1 input pin note: * before entering power-down mode, if this pin is set to si 1 input by bit si1 in pmr2, it should be kept from floating by external connection or should be set to general i/o use by clearing bit si1 to 0 prior to the state transition. 133 table 7-24 port 9 pin functions (cont) pin pin functions and selection method p9 1 /sck 1 functions are switched as follows by means of bit sck1 in pmr2, * bits smr13 to smr10 in serial mode register 1 (smr1) * , and bit pcr9 1 in pcr9. sck1 0 1 smr13 to 10 not 1111 1111 pcr9 1 01 pin function p9 1 input pin p9 1 output pin sck 1 output pin sck 1 input pin note: * before entering power-down mode, if this pin is set to sck 1 input by bit sck1 in pmr2 and bits smr13 to smr10 in smr1, it should be kept from floating by external connection, or else should be set to some other use by changing the sck1 bit or bits smr13 to smr10 prior to the state transition. for the settings of bits smr13 to smr10 in smr1, see 10.2.1, serial mode register 1 (smr1). p9 0 /pwm functions are switched as follows by means of bit pwm in pmr2 and bit pcr9 0 in pcr9. pwm 0 1 pcr9 0 01 pin function p9 0 input pin p9 0 output pin pwm output pin 7.8.4 pin states table 7-25 shows the port 9 pin states in each operating mode. table 7-25 port 9 pin states pins reset sleep standby watch subactive active p9 7 /ud, high previous high high high normal p9 6 /so 2 , impedance or state impedance impedance impedance operation p9 5 /si 2 /cs, pulled up retained p9 4 /sck 2 , p9 3 /so 1 , p9 2 /si 1 , p9 1 /sck 1 , p9 0 /pwm 134 section 8 timers 8.1 overview the h8/3714 series provides on-chip two prescalers (prescaler s and prescaler w) with different input clocks, and five timers (timers a through e). prescaler s is a 13-bit counter clocked by the system clock ( f = f osc /2). its prescaled outputs are used by timers a to c and timer e. prescaler w is a 5-bit counter clocked by the subclock ( f sub = f x /8). its prescaled output is used for time-base operation by timer a. table 8-1 outlines the functions of timers a through e. table 8-1 timer a to e functions operating clock event waveform name functions (internal) input pin output pin remarks timer a 8-bit interval timer f /8 to f /8192 (choice of 8 sources) time base f sub /32 (choice of 4 overflow periods) timer b 8-bit reloadable timer p1 0 /irq 0 interval timer event counter timer c 8-bit reloadable timer p1 1 /irq 1 interval timer event counter choice of up- or down-counting timer d 8-bit event counter p1 6 / event timer e 8-bit reloadable timer interval timer can output square wave with 50% duty cycle counting direction can be controlled by software or hardware. f /8 to f /8192 (choice of 7 sources) f /8 to f /8192 (choice of 8 sources) p1 5 /irq 5 / tmoe f /8 to f /8192 (choice of 7 sources) 135 8.1.1 prescaler operation 1. prescaler s (pss) prescaler s is a 13-bit counter using the system clock ( f = f osc /2) as its input clock. each input clock cycle causes prescaler s to increment once. prescaler s is initialized to h'0000 by a reset, and starts counting upon return to active mode. in standby mode, watch mode, and subactive mode, the system clock ( f ) pulse generator stops, so prescaler s also stops functioning. its value is reset to h'0000. the cpu cannot read or write prescaler s data. the output from prescaler s is shared by timers a to c and e as well as serial communication interfaces 1 and 2. the frequency division ratio can be set separately for each on-chip peripheral function. 2. prescaler w (psw) prescaler w is a 5-bit counter using the subclock ( f sub = f x /8) as its input clock. prescaler w is initialized to h'00 by a reset, and starts counting upon return to active mode. even in standby mode, watch mode, or subactive mode, prescaler w continues functioning so long as clock signals are supplied to pins x 1 and x 2 . prescaler w can be reset by setting bits tma3 and tma2 to 1 in timer mode register a (tma). the output from prescaler w can be used as the clock source for timer a, in which case timer a functions as a time base. figure 8-1 shows the clock signals supplied by prescalers s and w to peripheral modules. 136 figure 8-1 clock supply /2 to /8192 subclock pulse generator subclock divider 1/8 ff sub f /32 osc 1 osc 2 x 1 x 2 f x f osc system clock pulse generator f sub cpu, rom, ram, registers, flags, i/o prescaler s prescaler w timer a timers a to c and e; serial communication interfaces 1 and 2 system clock selection (lson bit in system control register 1) f system clock divider 1/2 137 8.2 timer a 8.2.1 overview timer a is an 8-bit interval timer. it can be connected to a 32.768 khz crystal oscillator for use as a real-time clock time base. 1. features features of timer a are given below. choice of eight internal clock sources ( f /8192, f /4096, f /2048, f /512, f /256, f /128, f /32, f /8). choice of four overflow periods (2 s, 1 s, 0.5 s, 125 ms) when timer a is used as a time base (using a 32.768 khz crystal oscillator). an interrupt is requested when the counter overflows. 2. block diagram figure 8-2 shows a block diagram of timer a. figure 8-2 block diagram of timer a 1/8 prescaler w (psw) prescaler s (pss) tma tca internal data bus f sub /32 f sub f /8192, /4096, /2048 /512, /256, /128, /32, /8 ff f ff ff 16 * 64 128 * * 256 irrta 32 khz crystal oscillator notation: tma: tca: irrta: timer mode register a timer counter a timer a overflow interrupt request flag (interrupt request register 2) * can be selected only when the input clock to tca is the output from prescaler w ( /32). f sub note: interval timer overflow * 1/2 f system clock 138 3. register configuration table 8-2 shows the register configuration of timer a. table 8-2 timer a registers name abbrev. r/w initial value address timer mode register a tma r/w h'f0 h'ffc0 timer counter a tca r h'00 h'ffc1 8.2.2 register descriptions 1. timer mode register a (tma) tma is an 8-bit read/write register for selecting the prescaler and input clock. upon reset, tma is initialized to h'f0. bits 7 to 4: reserved bits bits 7 to 4 are reserved; they always read 1, and cannot be modified. bit 3: prescaler select (tma3) bit 3 selects either prescaler s or prescaler w as the clock input source for timer a. bit 3 tma3 description 0 prescaler s (pss) is clock input source for timer a. (initial value) 1 prescaler w (psw) is clock input source for timer a. bit initial value read/write 7 1 6 1 5 1 4 1 3 tma3 0 r/w 0 tma0 0 r/w 2 tma2 0 r/w 1 tma1 0 r/w 139 bits 2 to 0: clock select (tma2 to tma0) bits 2 to 0 select the clock input to tca. the selection is made as follows by the combination of these bits and bit tma3. bit 3 bit 2 bit 1 bit 0 tma3 tma2 tma1 tma0 description prescaler divider ratio (interval timer) operation mode or overflow period (time base) 0000 pss, f /8192 (initial value) 1 pss, f /4096 1 0 pss, f /2048 1 pss, f /512 1 0 0 pss, f /256 1 pss, f /128 1 0 pss, f /32 1 pss, f 8 1000 psw, 2 s 1 psw, 1 s 1 0 psw, 0.5 s 1 psw, 125 ms 1 0 0 psw and tca are reset 1 10 1 note: f = f osc /2 interval timer mode time-base mode 140 2. timer counter a (tca) tca is an 8-bit read-only up-counter, which is incremented by internal clock input. the clock source for input to this counter is selected by bits tma3 to tma0 in timer mode register a (tma). the tca value can be read by the cpu at any time. tca is cleared by setting bits tma3 and tma2 of tma to 1. when tca overflows, the irrta bit in interrupt request register 2 (irr2) is set to 1. upon reset, tca is initialized to h'00. 8.2.3 timer operation timer a is an 8-bit timer which can be used either as an interval timer or, if a 32.768 khz crystal oscillator is connected, as a real-time clock time base. 1. interval timer operation when bit tma3 in timer mode register a (tma) is cleared to 0, timer a functions as an 8-bit interval timer. upon reset, tca is cleared to h'00 and bit tma3 is cleared to 0, so up-counting and interval timing resume immediately after the reset. the clock input to timer a is selected by bits tma2 to tma0 in tma; any of eight internal clock signals output by prescaler s can be selected. after the count value in tca reaches h'ff, the next clock signal input causes timer a to overflow, setting bit irrta to 1 in interrupt request register 2 (irr2). if ienta = 1 in interrupt enable register 2 (ienr2), a cpu interrupt is requested.* at overflow, tca returns to h'00 and starts counting up again. in this mode timer a functions as an interval timer that generates an overflow output at intervals of 256 input clock pulses. note: * for details on interrupts, see 3.2.2, interrupts. bit initial value read/write 7 tca7 0 r 6 tca6 0 r 5 tca5 0 r 4 tca4 0 r 3 tca3 0 r 0 tca0 0 r 2 tca2 0 r 1 tca1 0 r 141 2. real-time clock time base operation when bit tma3 in tma is set to 1, timer a functions as a time base for a real-time clock by counting clock signals output by prescaler w. the overflow period of timer a is set by bits tma1 and tma0 in tma. a choice of four periods is available. 3. count initialization when bits tma3 and tma2 are both set to 1, psw and tca are initialized (cleared to 0 and stopped). from this initialized state, if bit tma3 is left set to 1 and bit tma2 is cleared to 0, timer a begins counting from 0 in time base mode. from the initialized state, if bit tma3 is cleared to 0, timer a begins counting from 0 in interval timer mode. (bit tma2 can be either set or cleared.) however, since prescaler s (pss) has not been initialized, the time between clearing bit tma3 to 0 and the first count will vary. 142 8.3 timer b 8.3.1 overview timer b is an 8-bit up-counter that increments each time a clock pulse is input. this timer has two operation modes, interval and auto reload. 1. features features of timer b are given below. choice of seven internal clock sources ( f /8192, f /2048, f /512, f /256, f /128, f /32, f /8) or an external clock (can be used to count external events). an interrupt is requested when the counter overflows. 2. block diagram figure 8-3 shows a block diagram of timer b. figure 8-3 block diagram of timer b prescaler s (13 bits) tmb tcb tlb internal data bus f irq 0 irrtb notation: tmb: tcb: tlb: irrtb: timer mode register b timer counter b timer load register b timer b overflow interrupt request flag (interrupt request register 2) 143 3. pin configuration table 8-3 shows the timer b pin configuration. table 8-3 pin configuration name abbrev. i/o function event input pin p1 0 /irq 0 input timer b event input 4. register configuration table 8-4 shows the register configuration of timer b. table 8-4 timer b registers name abbrev. r/w initial value address timer mode register b tmb r/w h'78 h'ffc2 timer counter b tcb r h'00 h'ffc3 timer load register b tlb w h'00 h'ffc3 8.3.2 register descriptions 1. timer mode register b (tmb) tmb is an 8-bit read/write register for selecting the auto-reload function and input clock. upon reset, tmb is initialized to h'78. bit 7: auto-reload function select (tmb7) bit 7 selects the auto-reload function of timer b. bit 7 tmb7 description 0 interval timer function selected. (initial value) 1 auto-reload function selected. bit initial value read/write 7 tmb7 0 r/w 6 1 5 1 4 1 3 1 0 tmb0 0 r/w 2 tmb2 0 r/w 1 tmb1 0 r/w 144 bits 6 to 3: reserved bits bits 6 to 3 are reserved; they always read 1, and cannot be modified. bits 2 to 0: clock select (tmb2 to tmb0) bits 2 to 0 select the clock input to tcb. for external clock counting, either the rising or falling edge can be selected. bit 2 bit 1 bit 0 tmb2 tmb1 tmb0 description 0 0 0 internal clock: f /8192. (initial value) 0 0 1 internal clock: f /2048. 0 1 0 internal clock: f /512. 0 1 1 internal clock: f /256. 1 0 0 internal clock: f /128. 1 0 1 internal clock: f /32. 1 1 0 internal clock: f /8. 1 1 1 external clock (p1 0 /irq 0 ): rising or falling edge. * note: * the edge of the external event signal is selected by bit ieg0 in the irq edge select register (iegr). for details see 3.2.3 (2), irq edge select register (iegr). 2. timer counter b (tcb) tcb is an 8-bit read-only up-counter, which is incremented by internal or external clock input. the clock source for input to this counter is selected by bits tmb2 to tmb0 in timer mode register b (tmb). the tcb value can be read by the cpu at any time. when tcb overflows from h'ff to h'00 or to the value set in tlb, the irrtb bit in interrupt request register 2 (irr2) is set to 1. tcb is allocated to the same address as timer load register b (tlb). upon reset, tcb is initialized to h'00. bit initial value read/write 7 tcb7 0 r 6 tcb6 0 r 5 tcb5 0 r 4 tcb4 0 r 3 tcb3 0 r 0 tcb0 0 r 2 tcb2 0 r 1 tcb1 0 r 145 3. timer load register b (tlb) tlb is an 8-bit write-only register for setting the reload value of timer counter b (tcb). when a reload value is set in tlb, the same value is loaded into timer counter b (tcb) as well, and tcb starts counting up from that value. when tcb overflows during operation in auto- reload mode, the tlb value is loaded in tcb. accordingly, overflow periods can be set within the range of 1 to 256 input clocks. the same address is allocated to tlb as to tcb. upon reset, tlb is initialized to h'00. 8.3.3 timer operation timer b is an 8-bit multifunction timer. it can be used as an interval timer, an auto-reload timer, or an event counter. (event counting requires an input pin setting.) 1. timer b operation modes timer b is an 8-bit up-counter which is incremented each time a clock pulse is input. the two operation modes, interval and auto-reload, are explained below. interval timer operation when bit tmb7 in timer mode register b (tmb) is cleared to 0, timer b functions as an 8-bit interval timer. upon reset, tcb is cleared to h'00 and bit tmb7 is cleared to 0, so up-counting and interval timing resume immediately after the reset. the clock input to timer b is selected from seven internal clock signals output by prescaler s, or an external clock input at pin p1 0 /irq 0 . the selection is made by bits tmb2 to tmb0 of tmb. after the count value in tcb reaches h'ff, the next clock signal input causes timer b to overflow, setting bit irrtb to 1 in interrupt request register 2 (irr2). if ientb = 1 in interrupt enable register 2 (ienr2), a cpu interrupt is requested.* at overflow, tcb returns to h'00 and starts counting up again. during interval timer operation (tmb7 = 0), when a value is set in timer load register b (tlb), the same value is set in tcb. note: * for details on interrupts, see 3.2.2, interrupts. bit initial value read/write 7 tlb7 0 w 6 tlb6 0 w 5 tlb5 0 w 4 tlb4 0 w 3 tlb3 0 w 0 tlb0 0 w 2 tlb2 0 w 1 tlb1 0 w 146 auto-reload timer operation setting bit tmb7 in tmb to 1 causes timer b to function as an 8-bit auto-reload timer. when a reload value is set in tlb, the same value is loaded into tcb, becoming the value from which tcb starts its count. after the count value in tcb reaches h'ff, the next clock signal input causes timer b to overflow. the tlb value is then loaded into tcb, and the count continues from that value. the overflow period can be set within a range from 1 to 256 input clocks, depending on the tlb value. the clock sources and interrupts in auto-reload mode are the same as for interval mode. in auto-reload mode (bit tmb7 = 1), setting a new tlb value also initializes tcb. 2. operation on external clock timer b can operate on an external clock input as an event signal at pin p1 0 /irq 0 . external clock operation is selected by setting bits tmb2 to tmb0 in timer mode register b to all 1 s (111). tcb can count either rising or falling edges of the input at pin p1 0 /irq 0 . when timer b is used to count external event input, bit irqc0 in port mode register 1 (pmr1) should be set to 1, and bit ien0 in interrupt enable register 1 (ienr1) should be cleared to 0 to disable irq 0 interrupt requests. 147 8.4 timer c 8.4.1 overview timer c is an 8-bit up/down counter that increments or decrements each time a clock pulse is input. this timer has two operation modes, interval and auto reload. 1. features features of timer c are given below. choice of seven internal clock sources ( f /8192, f /2048, f /512, f /256, f /128, f /32, f /8) or an external clock (can be used to count external events). an interrupt is requested when the counter overflows. can be switched between up- and down-counting by software or hardware control. 2. block diagram figure 8-4 shows a block diagram of timer c. figure 8-4 block diagram of timer c internal data bus prescaler s tmc tcc tlc irrtc ud irq 1 f notation: tmc: tcc: tlc: irrtc: timer mode register c timer counter c timer load register c timer c overflow interrupt request flag (interrupt request register 2) 148 3. pin configuration table 8-5 shows the timer c pin configuration. table 8-5 pin configuration name abbrev. i/o function event input pin p1 1 /irq 1 input timer c event input up/down select pin p9 7 /ud input timer c counting direction control 4. register configuration table 8-6 shows the register configuration of timer c. table 8-6 timer c registers name abbrev. r/w initial value address timer mode register c tmc r/w h'18 h'ffc4 timer counter c tcc r h'00 h'ffc5 timer load register c tlc w h'00 h'ffc5 8.4.2 register descriptions 1. timer mode register c (tmc) tmc is an 8-bit read/write register for selecting the auto-reload function, counting direction, and input clock. upon reset, tmc is initialized to h'18. bit initial value read/write 7 tmc7 0 r/w 6 tmc6 0 r/w 5 tmc5 0 r/w 4 1 3 1 0 tmc0 0 r/w 2 tmc2 0 r/w 1 tmc1 0 r/w 149 bit 7: auto-reload function select (tmc7) bit 7 selects the auto-reload function of timer c. bit 7 tmc7 description 0 interval timer function selected. (initial value) 1 auto-reload function selected. bit 6: counter up/down control 1 (tmc6) this bit selects whether the counting direction of timer counter c (tcc) is controlled by hardware using pin p9 7 /ud, or by software using bit tmc5. bit 5: counter up/down control 2 (tmc5) this bit selects whether tcc is an up-counter or down-counter. the setting of this bit is valid when bit tmc6 = 0. bits tmc6 and tmc5 operate as follows. bit 6 bit 5 tmc6 tmc5 description 0 0 tcc is an up-counter. (initial value) 0 1 tcc is a down-counter. 1 * tcc up/down control is by input at pin p9 7 /ud. tcc is a down-counter if ud input is high, and an up-counter if ud input is low. note: * don? care. bits 4 and 3: reserved bits bits 4 and 3 are reserved; they always read 1, and cannot be modified. bits 2 to 0: clock select (tmc2 to tmc0) 150 bits 2 to 0 select the clock input to tcc. for external clock counting, either the rising or falling edge can be selected. bit 2 bit 1 bit 0 tmc2 tmc1 tmc0 description 0 0 0 internal clock: f /8192. (initial value) 0 0 1 internal clock: f /2048. 0 1 0 internal clock: f /512. 0 1 1 internal clock: f /256. 1 0 0 internal clock: f /128. 1 0 1 internal clock: f /32. 1 1 0 internal clock: f /8. 1 1 1 external clock (p1 1 /irq 1 ): rising or falling edge. * note: * the edge of the external clock is selected by bit ieg1 in the irq edge select register (iegr). for details see 3.2.3 2, irq edge select register (iegr). 2. timer counter c (tcc) tcc is an 8-bit read-only up-/down-counter, which is incremented or decremented by internal or external clock input. the clock source for input to this counter is selected by bits tmc2 to tmc0 in timer mode register c (tmc). the tcc value can be read by the cpu at any time. when tcc overflows (from h'ff to h'00 or to the value set in tlc) or underflows (from h'00 to h'ff or to the value set in tlc), the irrtc bit in interrupt request register 2 (irr2) is set to 1. tcc is allocated to the same address as timer load register c (tlc). upon reset, tcc is initialized to h'00. bit initial value read/write 7 tcc7 0 r 6 tcc6 0 r 5 tcc5 0 r 4 tcc4 0 r 3 tcc3 0 r 0 tcc0 0 r 2 tcc2 0 r 1 tcc1 0 r 151 3. timer load register c (tlc) tlc is an 8-bit write-only register for setting the reload value of tcc. when a reload value is set in tlc, the same value is loaded into timer counter c (tcc) as well, and tcc starts counting up or down from that value. when tcc overflows or underflows during operation in auto-reload mode, the tlc value is loaded in tcc. accordingly, overflow and underflow periods can be set within the range of 1 to 256 input clocks. the same address is allocated to tlc as to tcc. upon reset, tlc is initialized to h'00. 8.4.3 timer operation timer c is an 8-bit multifunction timer. it can be used as an interval timer, an auto-reload timer, or an event counter. (event counting requires an input pin setting.) 1. timer c operation modes timer c is an 8-bit up-/down-counter which is incremented or decremented each time a clock pulse is input. the two operation modes, interval and auto-reload, are explained below. interval timer operation when bit tmc7 in timer mode register c (tmc) is cleared to 0, timer c functions as an 8-bit interval timer. upon reset, timer counter c (tcc) is initialized to h'00 and tmc to h'18, so up-counting and interval timing resume immediately after the reset. the clock input to timer c is selected from seven internal clock signals output by prescaler s, or an external clock input at pin p1 1 /irq 1 . the selection is made by bits tmc2 to tmc0 in tmc. either software or hardware can control whether tcc counts up or down. the selection is made by tmc bits tmc6 and tmc5. bit initial value read/write 7 tlc7 0 w 6 tlc6 0 w 5 tlc5 0 w 4 tlc4 0 w 3 tlc3 0 w 0 tlc0 0 w 2 tlc2 0 w 1 tlc1 0 w 152 after the count value in tcc reaches h'ff (h'00), the next clock signal input causes timer c to overflow (underflow), setting bit irrtc to 1 in interrupt request register 2 (irr2). if bit ientc = 1 in interrupt enable register 2 (ienr2), a cpu interrupt is requested.* at overflow or underflow, tcc returns to h'00 or h'ff and starts counting up or down again. during interval timer operation (tmc7 = 0), when a value is set in timer load register c (tlc), the same value is set in tcc. note: * for details on interrupts, see 3.2.2, interrupts. auto-reload timer operation setting bit tmc7 in tmc to 1 causes timer c to function as an 8-bit auto-reload timer. when a reload value is set in tlc, the same value is loaded into tcc, becoming the value from which tcc starts its count. after the count value in tcc reaches h'ff (h'00), the next clock signal input causes timer c to overflow (or underflow). the tlc value is then loaded into tcc, and the count continues from that value. the overflow (underflow) period can be set within a range from 1 to 256 input clocks, depending on the tlc value. the clock sources, up/down control, and interrupts in auto-reload mode are the same as for interval mode. in auto-reload mode (bit tmc7 = 1), setting a new tlc value also initializes tcc. 2. operation on external clock timer c can operate on an external clock input as an event signal at pin p1 1 /irq 1 . external clock operation is selected by setting bits tmc2 to tmc0 in timer mode register c to all 1 s (111). tcc can count either rising or falling edges of the input at pin p1 1 /irq 1 . when timer c is used to count external event input, bit irqc1 in port mode register 1 (pmr1) should be set to 1, and bit ien1 in interrupt enable register 1 (ienr1) should be cleared to 0 to disable irq 1 interrupt requests. 3. tcc up/down control by hardware the counting direction of timer c can be controlled by input at pin p9 7 /ud. when bit tmc6 in tmc is set to 1, high-level input at the ud pin selects down-counting, while low-level input selects up-counting. when using input at pin ud for this control function, set the up/down bit in port mode register 2 (pmr2) to 1. 153 8.5 timer d 8.5.1 overview timer d is an 8-bit event counter, which is incremented by input of an external event signal. either rising or falling edges of the external event signal can be counted. 1. features features of timer d are given below. choice of rising or falling edge for external event counting. an interrupt is requested when the counter overflows. 2. block diagram figure 8-5 shows a block diagram of timer d. figure 8-5 block diagram of timer d internal data bus tmd tcd event irrtd notation: tmd: tcd: irrtd: timer mode register d timer counter d timer d overflow interrupt request flag (interrupt request register 2) 154 3. pin configuration table 8-7 shows the timer d pin configuration. table 8-7 pin configuration name abbrev. i/o function event input pin p1 6 / event input timer d event input 4. register configuration table 8-8 shows the register configuration of timer d. table 8-8 timer d registers name abbrev. r/w initial value address timer mode register d tmd r/w * h'7e h'ffc6 timer counter d tcd r h'00 h'ffc7 note: * writing to bit 7 of tmd is possible only when writing 1 to clear the counter. 8.5.2 register descriptions 1. timer mode register d (tmd) tmd is an 8-bit read/write register for clearing timer counter d (tcd), and for selecting whether input at the external event pin is sensed at the rising or falling edge. bit 7: counter clear (clr) bit 7 initializes tcd to h'00. bit 7 clr description 0 after 1 is written to this bit to initialize tcd, it is cleared to 0 by (initial value) hardware. 1 initializes tcd to h'00. bit initial value read/write 7 clr 0 w 6 1 5 1 4 1 3 1 0 edg 0 r/w 2 1 1 1 155 bits 6 to 1: reserved bits bits 6 to 1 are reserved; they always read 1, and cannot be modified. bit 0: edge select (edg) bit 0 selects the rising or falling edge of input at external event pin p1 6 / event . bit 0 edg description 0 tcd counts falling edges of input at pin p1 6 / event . (initial value) 1 tcd counts rising edges of input at pin p1 6 / event . 2. timer counter d (tcd) tcd is an 8-bit read-only up-counter, which is incremented by external clock input at pin p1 6 / event . the input clock edge is selected by the edg bit in timer mode register d (tmd). the tcd value can be read by the cpu at any time. when tcd overflows from h'ff to h'00, the irrtd bit in interrupt request register 2 (irr2) is set to 1. upon reset, tcd is initialized to h'00. bit initial value read/write 7 tcd7 0 r 6 tcd6 0 r 5 tcd5 0 r 4 tcd4 0 r 3 tcd3 0 r 0 tcd0 0 r 2 tcd2 0 r 1 tcd1 0 r 156 8.5.3 timer operation 1. operation on external clock timer d operates on an external clock input at pin p1 6 / event , used as an event input pin. the rising or falling edge of this input is selected by the edg bit in timer mode register d (tmd). after the count value in tcd reaches h'ff, the next clock signal input causes timer d to overflow, setting bit irrtd in interrupt request register 2 (irr2) to 1 . if bit ientd = 1 in interrupt enable register 2 (ienr2), a cpu interrupt is requested.* at overflow, tcd returns to h'00 and starts counting up again. tcd can be cleared by setting the clr bit to 1 in tmd. to use external event input, the event bit in port mode register 1 (pmr1) must be set to 1. note: * for details on interrupts, see 3.2.2, interrupts. 157 8.6 timer e 8.6.1 overview timer e is an 8-bit up-counter that increments each time a clock pulse is input. this timer has two operation modes, interval and auto reload. in addition, it can output a square wave with a 50% duty cycle, using overflow signals or signals from prescaler s. 1. features features of timer e are given below. choice of eight internal clock sources ( f /8192, f /4096, f /2048, f /512, f /256, f /128, f /32, f /8). an interrupt is requested when the counter overflows. prescaler signals can provide a fixed-frequency output with a 50% duty cycle. when f = 4 mhz, output is 1.95 khz or 3.9 khz. when f = 2 mhz, output is 0.98 khz or 1.95 khz. overflow signals can produce square wave output of any frequency with a 50% duty cycle. 158 2. block diagram figure 8-6 shows a block diagram of timer e. figure 8-6 block diagram of timer e 3. pin configuration table 8-9 shows the timer e pin configuration. table 8-9 pin configuration name abbrev. i/o function timer e waveform output pin p1 5 /irq 5 /tmoe output timer e output internal data bus irrte f tle tce tme prescaler s notation: tme: tce: tle: irrte: timer mode register e timer counter e timer load register e timer e overflow interrupt request flag (interrupt request register 2) tmoe output latch 159 4. register configuration table 8-10 shows the register configuration of timer e. table 8-10 timer e registers name abbrev. r/w initial value address timer mode register e tme r/w h'78 h'ffc8 timer counter e tce r h'00 h'ffc9 timer load register e tle w h'00 h'ffc9 port mode register 4 pmr4 r/w h'0f h'ffee 8.6.2 register descriptions 1. timer mode register e (tme) tme is an 8-bit read/write register for selecting the auto-reload function and input clock. upon reset, tme is initialized to h'78. bit 7: auto-reload function select (tme7) bit 7 selects the auto-reload function of timer e. bit 7 tme7 description 0 interval timer function selected. (initial value) 1 auto-reload function selected. bits 6 to 3: reserved bits bits 6 to 3 are reserved; they always read 1, and cannot be modified. bit initial value read/write 7 tme7 0 r/w 6 1 5 1 4 1 3 1 0 tme0 0 r/w 2 tme2 0 r/w 1 tme1 0 r/w 160 bits 2 to 0: clock select (tme2 to tme0) bits 2 to 0 select the clock input to tce. bit 2 bit 1 bit 0 tme2 tme1 tme0 description 0 0 0 internal clock: f /8192. (initial value) 0 0 1 internal clock: f /4096. 0 1 0 internal clock: f /2048. 0 1 1 internal clock: f /512. 1 0 0 internal clock: f /256. 1 0 1 internal clock: f /128. 1 1 0 internal clock: f /32. 1 1 1 internal clock: f /8. 2. timer counter e (tce) tce is an 8-bit read-only up-counter, which is incremented by internal clock input. the clock source for input to this counter is selected by bits tme2 to tme0 in timer mode register e (tme). the tce value can be read by the cpu at any time. when tce overflows from h'ff to h'00 or to the value set in tle, the irrte bit in interrupt request register 2 (irr2) is set to 1. tce is allocated to the same address as timer load register e (tle). upon reset, tce is initialized to h'00. bit initial value read/write 7 tce7 0 r 6 tce6 0 r 5 tce5 0 r 4 tce4 0 r 3 tce3 0 r 0 tce0 0 r 2 tce2 0 r 1 tce1 0 r 161 3. timer load register e (tle) tle is an 8-bit write-only register for setting the reload value of tce. when a reload value is set in tle, the same value is loaded into timer counter e (tce) as well, and tce starts counting up from that value. when tce overflows during operation in auto-reload mode, the tle value is loaded in tce. accordingly, the overflow period can be set within the range of 1 to 256 input clocks. the same address is allocated to tle as to tce. upon reset, tle is initialized to h'00. 4. port mode register 4 (pmr4) pmr4 is an 8-bit read/write register, for switching functions of pin p1 5 /irq 5 /tmoe and for controlling waveform output from pin tmoe. upon reset, pmr4 is initialized to h'0f. bit initial value read/write 7 tle7 0 w 6 tle6 0 w 5 tle5 0 w 4 tle4 0 w 3 tle3 0 w 0 tle0 0 w 2 tle2 0 w 1 tle1 0 w bit initial value read/write 7 teo 0 r/w 6 teo on 0 r/w 5 freq 0 r/w 4 vrfr 0 r/w 3 1 0 1 2 1 1 1 162 bit 7: timer e output select (teo) bit 6: timer e output on/off (teo on) bit 5: fixed frequency select (freq) bit 4: variable frequency select (vrfr) p1 5 /irq 5 /tmoe pin functions are switched as follows, by means of bits 7 to 4 of pmr4 and bit irqc5 of port mode register 1 (pmr1). pmr1 pmr4 description bit 5 bit 7 bit 6 bit 5 bit 4 irqc5 teo teo on freq vrfr pin function pin state 00000p1 5 pin standard i/o port (initial value) 00 *** p1 5 pin standard i/o port 010 ** tmoe output pin low-level output (off) 01100 tmoe output pin fixed-frequency output: (on) ( f /2048) 1.95 khz ( f = 4 mhz) 0.98 khz ( f = 2 mhz) 01110 tmoe output pin fixed-frequency output: (on) ( f /1024) 3.9 khz ( f = 4 mhz) 1.95 khz ( f = 2 mhz) 011 * 1 tmoe output pin variable-frequency output: (on) toggled by timer e overflow 1 **** irq 5 input pin external interrupt input note: * don? care. bits 3 to 0: reserved bits bits 3 to 0 are reserved; they always read 1, and cannot be modified. 163 8.6.3 timer operation timer e is an 8-bit up-counter that is incremented each time a clock pulse is input. it functions as an interval or auto-reload timer. it can also output a square wave having a 50% duty cycle. each of these operation modes is explained below. 1. interval timer operation when bit tme7 in timer mode register e (tme) is cleared to 0, timer e functions as an 8-bit interval timer. upon reset, timer counter e (tce) is reset to h'00 and bit tme7 is cleared to 0, so up- counting and interval timing resume immediately after the reset. the clock input to timer e is selected from eight internal clock signals output by prescaler s. the selection is made by bits tme2 to tme0 in tme. after the count value in tce reaches h'ff, the next clock signal input causes timer e to overflow, setting bit irrte to 1 in interrupt request register 2 (irr2). if bit iente = 1 in interrupt enable register 2 (ienr2), a cpu interrupt is requested.* at overflow, tce returns to h'00, and starts counting up again. during interval timer operation (tme7 = 0), when a value is set in timer load register e (tle), the same value is set in tce. note: * for details on interrupts, see 3.2.2, interrupts. 2. auto-reload timer operation setting bit tme7 in tme to 1 causes timer e to function as an 8-bit auto-reload timer. when a reload value is set in tle, the same value is loaded into tce, becoming the value from which tce starts its count. after the count value in tce reaches h'ff, the next clock signal input causes timer e to overflow. the tle value is then loaded into tce, and the count continues from that value. the overflow period can be set within a range from 1 to 256 input clocks, depending on the tle value. the clock sources and interrupts in auto-reload mode are the same as for interval mode. in auto-reload mode (bit tme7 = 1), setting a new tle value also initializes tce. 164 3. square wave output a 50% duty square wave can be output at pin p1 5 /irq 5 /tmoe if this function is selected in port mode register 4 (pmr4) and bit irqc5 in port mode register 1 (pmr1). when bit vrfr = 0 in pmr4, the square wave has a fixed frequency designated in the freq bit. for the frequencies that can be output, see 8.6.2 (4), port mode register 4 (pmr4). when bit vrfr = 1, timer e overflow generates a toggle output alternating between low and high level (see figure 8-7). the overflow period is selected in timer load register e (tle), with timer e operating in auto-reload mode (bit tme7 = 1). the operating clock can be selected by means of bits tme2 to tme0. these settings can give a waveform output of any desired frequency within the range shown in table 8-11. figure 8-7 square wave output generated by timer e overflow timer e value = h'ff tle value (auto-reload mode selected) tmoe output waveform timer e interrupt request 165 table 8-11 frequencies of output waveforms generated by timer e overflow output waveform ( f = 2 mhz) 1 count (tle = h'ff) 2 256 counts (tle = h'00) 2 internal clock count time output frequency count time output frequency f/ 8 (250 khz) 8 ? 125 kz 2024 ? 488.3 hz f /32 (62.5 khz) 32 ? 31.25 khz 8192 ? 122.1 hz f /128 (15.62 khz) 128 ? 7.8125 khz 32.768 ms 30.5 hz f /256 (7.8125 khz) 256 ? 3.9063 khz 65.536 ms 15.3 hz f /512 (3.9062 khz) 512 ? 1.9531 khz 131.072 ms 7.63 hz f /2048 (976.5 hz) 2.048 ms 488.3 hz 524.288 ms 1.91 hz f /4096 (488.2 hz) 4.096 ms 244.1 hz 1048.576 ms 0.95 hz f /8192 (244.1 hz) 8.192 ms 122.1 hz 2097.152 ms 0.477 hz output waveform ( f = 4 mhz) 1 count (tle = h'ff) 2 256 counts (tle = h'00) 2 internal clock count time output frequency count time output frequency f/ 8 (500 khz) 4 ? 250 kz 1024 ? 976.6 hz f /32 (125 khz) 16 ? 62.5 khz 4096 ? 244.1 hz f /128 (31.25 khz) 64 ? 15.625 khz 16.384 ms 61.0 hz f /256 (15.625 khz) 128 ? 7.8125 khz 32.768 ms 30.5 hz f /512 (7.8125 khz) 256 ? 3.9063 khz 65.536 ms 15.3 hz f /2048 (1.963 hz) 1.024 ms 976.6 hz 262.144 ms 3.8 hz f /4096 (976.52 hz) 2.048 ms 488.3 hz 524.288 ms 1.91 hz f /8192 (488.2 hz) 4.096 ms 244.1 hz 1048.576 ms 0.95 hz 166 8.7 interrupts timer a to e interrupts are requested when a timer overflows or underflows. each timer is assigned its own vector address. the priority of interrupts is in the order of timer a (high) to timer e (low). further details are given in 3.2.2, interrupts, table 3-2, interrupt sources. when timers a to e overflow, the corresponding bit irrta to irrte in interrupt request register 2 (irr2) is set to 1. these interrupt flags are not cleared even if the interrupt is accepted. they must be cleared to 0 by software in the interrupt handler routine. interrupts may be enabled or disabled independently for each timer by means of bits ienta to iente in interrupt enable register 2 (ienr2). for further details see 3.2.3, interrupt control registers. 8.8 application notes even when the event bit in port mode register 1 (pmr1) designates the p1 6 usage of pin p1 6 / event , reading the p1 6 pin may cause timer d to increment. when using timer d, be sure to clear timer counter d (tcd) by means of the clr bit in timer mode register d (tmd). 167 168 section 9 14-bit pwm 9.1 overview the h8/3714 series is provided with a 14-bit pwm (pulse width modulator) on-chip, which can be used as a d/a converter by connecting a low-pass filter. 9.1.1 features features of the 14-bit pwm are as follows. choice of two conversion periods a conversion period of 32768/ f , with a minimum modulation width of 2/ f (pwcr0 = 1), or a conversion period of 16384/ f , with a minimum modulation width of 1/ f (pwcr0 = 0), can be chosen. pulse division method for less ripple 9.1.2 block diagram figure 9-1 shows a block diagram of the 14-bit pwm. figure 9-1 block diagram of 14-bit pwm pwdrl pwdru pmr2 (bit 0) p9 /pwm 0 /2 f /4 f pwm waveform generator notation: pwdrl: pwdru: pwcr: pmr2: pwm data register l pwm data register u pwm control register port mode register 2 internal data bus pwcr 169 9.1.3 pin configuration table 9-1 shows the output pin assigned to the 14-bit pwm. table 9-1 pin configuration name abbrev. i/o function pwm waveform output pin pwm output pwm waveform output 9.1.4 register configuration table 9-2 shows the register configuration of the 14-bit pwm. table 9-2 register configuration name abbrev. r/w initial value address pwm control register pwcr w h'fe h'ffcc pwm data register u pwdru w h'c0 h'ffcd pwm data register l pwdrl w h'00 h'ffce 170 9.2 register descriptions 9.2.1 pwm control register (pwcr) pwcr is an 8-bit write-only register for input clock selection. upon reset, pwcr is initialized to h'fe. bits 7 to 1: reserved bits bits 7 to 1 are reserved; they always read 1, and cannot be modified. bit 0: clock select (pwcr0) bit 0 selects the clock supplied to the 14-bit pwm. this bit is a write-only bit; it always reads 1. bit 0 pwcr0 description 0 the input clock is f /2 (t f = 2/ f ). the conversion period is 16384/ f , (initial value) with a minimum modulation width of 1/ f . 1 the input clock is f /4 (t f = 4/ f ). the conversion period is 32768/ f , with a minimum modulation width of 2/ f . notation: t f : period of pwm input clock bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 pwcr0 0 w 2 1 1 1 171 9.2.2 pwm data registers u and l (pwdru, pwdrl) pwdru and pwdrl form a 14-bit write-only register, with the upper 6 bits assigned to pwdru and the lower 8 bits to pwdrl. the value written to pwdru and pwdrl gives the total high- level width of one pwm waveform cycle. when 14-bit data is written to pwdru and pwdrl, the register contents are latched in the pwm waveform generator, updating the pwm waveform generation data. the 14-bit data should always be written in the following sequence, first to pwdrl and then to pwdru. 1. write the lower 8 bits to pwdrl. 2. write the upper 6 bits to pwdru. pwdru and pwdrl are write-only registers. if they are read, all bits read 1. upon reset, pwdru and pwdrl are initialized to h'c000. bit initial value read/write 7 1 6 1 5 pwdru5 0 w 4 pwdru4 0 w 3 pwdru3 0 w 0 pwdru0 0 w 2 pwdru2 0 w 1 pwdru1 0 w pwdru bit initial value read/write 7 pwdrl7 0 w 6 pwdrl6 0 w 5 pwdrl5 0 w 4 pwdrl4 0 w 3 pwdrl3 0 w 0 pwdrl0 0 w 2 pwdrl2 0 w 1 pwdrl1 0 w pwdrl 172 9.3 operation when using the 14-bit pwm, set the registers in the following sequence. 1. set bit pwm in port mode register 2 (pmr2) to 1 so that pin p9 0 /pwm is designated for pwm output. 2. set bit pwcr0 in the pwm control register (pwcr) to select a conversion period of either 32768/ f (pwcr0 = 1) or 16384/ f (pwcr0 = 0). 3. set the output waveform data in pwm data registers u and l (pwdru/l). be sure to write in the correct sequence, first pwdrl then pwdru. when data is written to pwdru, the data in these registers will be latched in the pwm waveform generator, updating pwm waveform generation in synchronization with internal signals. one conversion period consists of 64 pulses, as shown in figure 9-2. the total of the high- level pulse widths during this period (t h ) corresponds to the data in pwdru and pwdrl. this relation can be represented as follows. t h = (data value in pwdru and pwdrl + 64) t f /2 where t f is the pwm input clock period, either 2/ f (bit pwcr0 = 0) or 4/ f (bit pwcr0 = 1). if the data value in pwdru and pwdrl is between h'3fc0 and h'3fff, the pwm output level will be high. when the data value is h'0000, t h = 64 t f /2 = 32 t f . example: settings in order to obtain a conversion period of 8,192 ?: when bit pwcr0 = 0, the conversion period is 16384/ f , so f must be 2 mhz. in this case t fn = 128 ?, with 1/ f (resolution) = 0.5 ?. when bit pwcr0 = 1, the conversion period is 32768/ f , so f must be 4 mhz. in this case t fn = 128 ?, with 2/ f (resolution) = 0.5 ?. accordingly, for a conversion period of 8,192 ?, the system clock frequency ( f ) must be 2 mhz or 4 mhz. 173 figure 9-2 pwm output waveform t h1 t h2 t h3 t h63 t h64 1 conversion period t f1 t f2 t f63 t = t = t . . . = t f1 f2 f3 f64 t = t + t + t + . . . + t h1 h2 h3 h64 h t f64 174 section 10 sci1 10.1 overview serial communication interface 1 (sci1) performs synchronous serial transfer of 8-bit or 16-bit data. 10.1.1 features sci1 features are as follows. choice of 8-bit or 16-bit data transfer choice of eight internal clock sources ( f /1024, f /256, f /64, f /32, f /16, f /8, f /4, f /2) or an external clock interrupts requested at completion of transfer or when error occurs 10.1.2 block diagram figure 10-1 shows a block diagram of sci1. figure 10-1 block diagram of sci1 f prescaler s (13 bits) smr1 octal/hexadecimal counter 1 (3 or 4 bits) spr1 sdrl1 sdru1 sck irrs1 so si 1 1 1 notation: smr1: spr1: sdrl1: sdru1: irrs1: serial mode register 1 serial port register 1 serial data register l1 serial data register u1 serial communication interface 1 interrupt request flag (interrupt request register 3) internal data bus 175 10.1.3 pin configuration table 10-1 shows the sci1 pin configuration. table 10-1 pin configuration name abbrev. i/o function sci1 clock pin sck 1 i/o sci1 clock input or output sci1 data input pin si 1 input sci1 received data input sci1 data output pin so 1 output sci1 transmit data output 10.1.4 register configuration table 10-2 shows the sci1 register configuration. table 10-2 sci1 registers name abbrev. r/w initial value address serial mode register 1 smr1 w h'80 h'ffb0 serial data register u1 sdru1 r/w not fixed h'ffb1 serial data register l1 sdrl1 r/w not fixed h'ffb2 serial port register 1 spr1 r/w not fixed h'ffb3 port mode register 2 pmr2 r/w h'00 h'ffec port mode register 3 pmr3 r/w h'97 h'ffed 176 10.2 register descriptions 10.2.1 serial mode register 1 (smr1) smr1 is an 8-bit write-only register, for selecting the operation mode and the prescaler divider ratio. another function is to initialize the internal state of the serial interface, which happens at each write access to smr1. when smr1 is written to, serial clock supply to serial data registers u1 and l1 (sdru1, sdrl1) and to the octal/hexadecimal counter is stopped, and the octal/hexadecimal counter is reset to h'00. accordingly, writing to the serial mode register while the serial interface is operating will abort data transmission or reception, and the serial communication interface 1 interrupt request flag (irrs1) will be set. upon reset, smr1 is initialized to h'80. bit 7: reserved bit bit 7 is reserved; it always reads 1, and cannot be modified. bits 6 to 4: operation mode select (smr16 to smr14) bits 6 to 4 select the sci1 operation mode. bit 6 bit 5 bit 4 smr16 smr15 smr14 description 0 0 0 continuous clock output mode (initial value) smr15, smr14 set to value other 8-bit transfer mode than 00 1 0 0 continuous clock output mode smr15, smr14 set to value other 16-bit transfer mode than 00 bit initial value read/write 7 1 6 smr16 0 w 5 smr15 0 w 4 smr14 0 w 3 smr13 0 w 0 smr10 0 w 2 smr12 0 w 1 smr11 0 w 177 bits 3 to 0: clock select (smr13 to smr10) bits 3 to 0 select the clock supplied to sci1. bit 3 bit 2 bit 1 bit 0 clock prescaler smr13 smr12 smr11 smr10 pin sck 1 source divider ratio 000 0sck 1 output prescaler s f /1024 256 512 (initial value) 1 sck 1 output prescaler s f /256 64 128 1 0 sck 1 output prescaler s f /64 16 32 1 sck 1 output prescaler s f /32 8 16 10 0sck 1 output prescaler s f /16 4 8 1 sck 1 output prescaler s f /8 2 4 1 0 sck 1 output prescaler s f /4 1 2 1 sck 1 output prescaler s f /2 1 1 0 0 0 not used 11 0 11 1sck 1 input external clock 10.2.2 serial data register u1 (sdru1) note: * not fixed sdru1 is an 8-bit read/write register. it is used as the data register for the upper 8 bits in 16-bit transfer (sdrl1 is used for the lower 8 bits). data written to sdru1 is output to sdrl1 starting from the least significant bit (lsb), in synchronization with the falling edge of the serial clock. this data is than replaced by lsb-first data input at pin si1, synchronized with the rising edge of the serial clock. in this way data is shifted in the direction from the most significant bit (msb) toward the lsb. sdru1 must be written or read only after data transmission or reception is complete. if this register is read or written while a data transfer is in progress, the data contents are not guaranteed. the sdru1 value upon reset is not fixed. serial clock period (?) f = 4 mhz f = 2 mhz bit initial value read/write 7 sdru17 r/w 6 sdru16 r/w 5 sdru15 r/w 4 sdru14 r/w 3 sdru13 r/w 0 sdru10 r/w 2 sdru12 r/w 1 sdru11 r/w * *** **** 178 10.2.3 serial data register l1 (sdrl1) note: * not fixed sdrl1 is an 8-bit read/write register. it is used as the data register in 8-bit transfer, and as the data register for the lower 8 bits in 16-bit transfer (sdru1 is used for the upper 8 bits). in 8-bit transfer, data written to sdrl1 is output from pin so1 starting from the least significant bit (lsb), in synchronization with the falling edge of the serial clock. this data is then replaced by lsb-first data input at pin si1, synchronized with the rising edge of the serial clock. in this way data is shifted in the direction from the most significant bit (msb) toward the lsb. in 16-bit transfer, operation is the same as for 8-bit transfer, except that input data is fed in via sdru1. sdrl1 must be written or read only after data transmission or reception is complete. if this register is read or written while a data transfer is in progress, the data contents are not guaranteed. the sdrl1 value upon reset is not fixed. 10.2.4 serial port register 1 (spr1) note: * not fixed spr1 is an 8-bit read/write register, bit 7 of which is connected to the last output stage of sdrl1. bit initial value read/write 7 sdrl17 r/w 6 sdrl16 r/w 5 sdrl15 r/w 4 sdrl14 r/w 3 sdrl13 r/w 0 sdrl10 r/w 2 sdrl12 r/w 1 sdrl11 r/w ******** bit initial value read/write 7 r/w 6 1 5 1 4 1 3 1 0 1 2 1 1 1 so1 last bit * 179 bit 7: extended data bit (so1 last bit) bit 7 holds the last bit of transmitted data after transmission ends. output from pin so1 can be altered by software by modifying this bit either before or after transmission. if this bit is written during data transmission, the data contents are not guaranteed. bit 7 so1 last bit description 0 output from pin so 1 is low. (initial value) 1 output from pin so 1 is high. bits 6 to 0: reserved bits bits 6 to 0 are reserved: they always read 1, and cannot be modified. 10.2.5 port mode register 2 (pmr2) pmr2 is an 8-bit read/write register, for switching the port 9 pin functions. bits 3 to 1, in combination with smr1, set the sci1 operation mode. upon reset, pmr2 is initialized to h'00. bits 3 to 1 are explained here. for bits 7 to 4 and bit 0, see 7.10.2 (1), port mode register 2 (pmr2). bit 3: pin p9 3 /so 1 function switch (so1) bit 3 selects whether pin p9 3 /so 1 functions as a p9 3 input/output pin or as the so 1 output pin. bit 3 so1 description 0 pin p9 3 /so 1 functions as p9 3 i/o pin. (initial value) 1 pin p9 3 /so 1 functions as so 1 output pin. setting bit sck1 to 1 and clearing bit si1 to 0 puts sci1 in transmit mode. bit initial value read/write 7 0 r/w 6 so2 0 r/w 5 si2 0 r/w 4 sck2 0 r/w 3 so1 0 r/w 0 pwm 0 r/w 2 si1 0 r/w 1 sck1 0 r/w up/ down 180 bit 2: pin p9 2 /si 1 function switch (si1) bit 2 selects whether pin p9 2 /si 1 functions as a p9 2 input/output pin or as the si 1 output pin. bit 2 si1 description 0 pin p9 2 /si 1 functions as p9 2 i/o pin. (initial value) 1 pin p9 2 /si 1 functions as si 1 output pin. setting bit sck1 to 1 and clearing bit so1 to 0 puts sci1 in receive mode. bit 1: pin p9 1 /sck 1 function switch (sck1) bit 1 selects whether pin p9 1 /sck 1 functions as a p9 1 input/output pin or as the sck 1 input/output pin. bit 1 sck1 description 0 pin p9 1 /sck 1 functions as p9 1 i/o pin. (initial value) 1 pin p9 1 /sck 1 functions as sck 1 i/o pin. the direction of clock i/o and the prescaler divider ratio are set in serial mode register 1 (smr1). 10.2.6 port mode register 3 (pmr3) pmr3 is an 8-bit read/write register, for enabling the pmos transistors of sci1 and sci2 data output pins (pins so 1 and so 2 ), and for controlling sci2 chip select output (pin si 2 / cs ). upon reset, pmr3 is initialized to h'97. bit 3 is explained here. for bits 6 and 5, see 11.2.5, port mode register 3 (pmr3). bit 3: pin so 1 pmos on/off (so1pmos) bit 3 enables or disables the pmos buffer transistor of pin p9 3 /so 1 . bit 3 s01pmos description 0 the pmos transistor of pin p9 3 /so 1 is enabled: cmos output. (initial value) 1 the pmos transistor of pin p9 3 /so 1 is disabled: nmos open-drain output. bit initial value read/write 7 1 6 0 r/w 5 cs 0 r/w 4 1 3 0 r/w 0 1 2 1 1 1 so2 pmos so1 pmos 181 10.3 operation 10.3.1 overview sci1 sends and receives data in synchronization with clock pulses. sci1 operation modes are set by bits 6 to 4 of serial mode register 1 (smr1) and bits 3 to 1 of port mode register 2 (pmr2) in combination, as shown in table 10-3. table 10-3 sci1 operation mode setting smr1 pmr2 smr16 smr15 smr14 pmr23 pmr22 pmr21 operation mode *** 0 0 0 serial communication disabled * 00001 continuous clock output mode 0 1 0 1 8-bit transmit mode 0 1 1 8-bit receive mode 1 1 1 8-bit transmit/receive mode 1 1 0 1 16-bit transmit mode 0 1 1 16-bit receive mode 1 1 1 16-bit transmit/receive mode note: * don? care. sci1 consists of smr1, serial data register u1 (sdru1), serial data register l1 (sdrl1), serial port register 1 (spr1), an octal/hexadecimal counter, and a multiplexer. (see figure 10-1.) pin sck 1 and the serial clock are controlled by writing data to smr1. sdru1 and sdrl1 are used to write transmit data and to hold received data; these registers can be written and read by software. data in these registers is shifted in synchronization with the serial clock, for input and output at pins si 1 and so 1 . sci1 operation starts with a dummy read of smr1. the octal/hexadecimal counter is cleared to h'0 by this dummy read, and starts counting anew from the falling edge of the serial clock (pin sck 1 ), being incremented by 1 at each rising edge of the serial clock. if 8 or 16 serial clock cycles are input and the counter overflows, or if data transmission or reception is aborted, the octal/hexadecimal counter is cleared to h'0. at the same time bit irrs1 in interrupt request register 3 (irr3) is set to 1. for more details on interrupts, see 3.2.2, interrupts. smr15, smr14 set to value other than 00 smr15, smr14 set to value other than 00 182 10.3.2 data transfer format figure 10-2 shows the synchronous data transfer format. data can be sent and received in lengths of 8 bits or 16 bits. data is sent and received starting from the least significant bit, in lsb-first format. transmit data is output from one falling edge of the serial clock until the next falling edge. receive data is latched at the rising edge of the serial clock. figure 10-2 synchronous data transfer format 10.3.3 clock eight internal clock sources or an external clock may be selected as the serial clock. when an internal clock is used, pin sck 1 is the clock output pin. 10.3.4 data transmit/receive 1. initializing sci1 before data is sent or received, first sci1 must be initialized by software. this is done by writing the desired transfer conditions in serial mode register 1 (smr1). 2. transmitting a transmit operation is carried out as follows. set bit so1 in port mode register 2 (pmr2) to 1, making pin p9 3 /so 1 the so 1 output pin. also set bit sck1 in pmr2 to 1, making pin p9 1 /sck 1 the sck 1 i/o pin. if necessary, set the so1pmos bit in pmr3 for nmos open-drain output at pin so 1 . bit 0 bit 1 bit 2 bit 3 bit n ?1 bit n sck so si input data latch timing lsb msb 1 1 1 n = 7: 8-bit transfer mode n = 15: 16-bit transfer mode 183 set bit smr16 in smr1 to 1 or 0, and set bits smr15 and smr14 to a value other than 00, designating 8- or 16-bit transfer mode. select the serial clock with bits smr13 to smr10. writing data to smr1 initializes the internal state of sci1. write transmit data in serial data register l1 (sdrl1) and serial data register u1 (sdru1), as follows. 8-bit transfer mode: sdrl1 16-bit transfer mode: upper byte in sdru1, lower byte in sdrl1 execute a dummy read of smr1. sci1 starts operating, and outputs the transmit data at pin so 1 . after data transmission is complete, bit irrs1 in interrupt request register 3 (irr3) is set to 1. when an internal clock source is used, a serial clock is output from pin sck 1 in synchronization with the transmit data. after data transmission is complete, the serial clock is not output until the next dummy read of smr1. during this time, pin so 1 continues to output the value of the last bit transmitted. when an external clock source is used, data is transmitted in synchronization with the serial clock input at pin sck 1 . after data transmission is complete, if the serial clock continues to be input, transmission resumes. between transmissions, the output value of pin so 1 can be changed by rewriting bit 7 (so1 last bit) in serial port register 1 (spr1). executing a dummy read of smr1 during transmission will cause a transmit error, setting bit irrs1 in irr3 to 1. 3. receiving a receive operation is carried out as follows. set bit si1 in port mode register 2 (pmr2) to 1, making pin p9 2 /si 1 the si 1 input pin. also set bit sck1 in pmr2 to 1, making pin p9 1 /sck 1 the sck 1 i/o pin. set bit smr16 in serial mode register 1 (smr1) to 1 or 0, and set bits smr15 and smr14 to a value other than 00, designating 8- or 16-bit transfer mode. select the serial clock with bits smr13 to smr10. writing data to smr1 initializes the internal state of sci1. execute a dummy read of smr1. sci1 starts operating, and receive data is input at pin si 1 . 184 after data reception is complete, bit irrs1 in interrupt request register 3 (irr3) is set to 1. read the received data from sdrl1 and sdru1, as follows. 8-bit transfer mode: sdrl1 16-bit transfer mode: upper byte in sdru1, lower byte in sdrl1 when an internal clock source is used, a dummy read of smr1 immediately starts a data receive operation. the serial clock is output from pin sck 1 . when an external clock source is used, after the dummy read of smr1, data is received in synchronization with the serial clock input at pin sck 1 . after data reception is complete, if the serial clock continues to be input, reception resumes. executing a dummy read of smr1 during reception will cause a receive error, setting bit irrs1 in irr3 to 1. 4. simultaneous transmit/receive a simultaneous transmit/receive operation is carried out as follows. set bits so1, si1, and sck1 in pmr2 to 1, designating the so 1 output pin, si 1 pin, and sck 1 pin functions. if necessary, set the so1pmos bit in pmr3 for nmos open-drain output at pin so 1 . set bit smr16 in smr1 to 1 or 0, and set bits smr15 and smr14 to a value other than 00, designating 8- or 16-bit transfer mode. select the serial clock with bits smr13 to smr10. writing data to smr1 initializes the internal state of sci1. write transmit data in sdrl1 and sdru1, as follows. 8-bit transfer mode: sdrl1 16-bit transfer mode: upper byte in sdru1, lower byte in sdrl1 execute a dummy read of smr1. sci1 starts operating: transmit data is output at pin so 1 , and receive data is input at pin si 1 . after data transmission and reception are complete, bit irrs1 in irr3 is set to 1. read the received data from sdrl1 and sdru1. 8-bit transfer mode: sdrl1 16-bit transfer mode: upper byte in sdru1, lower byte in sdrl1 185 in simultaneous data transmit/receive, the transmit operation and receive operation described in 10.3.4 sections 2 and 3 take place at the same time. see those sections for further details. during a transmit/receive operation, a dummy read of smr1 will result in a transmit/receive error, setting bit irrs1 in irr3 to 1. 10.3.5 sci1 state transitions sci1 has three internal states, as shown in figure 10-3. in the serial start pending state, the internal state of the serial communication interface is initialized. in this state, the serial communication interface does not operate even if a serial clock signal is input. executing a dummy read of smr1 changes this state to the serial clock pending state. in the serial clock pending state, when a serial clock signal is input the octal/hexadecimal counter starts counting up and the serial data register starts shifting, entering the transfer state. if continuous clock output mode has been selected, however, sci1 outputs the clock signal continuously and does not enter the transfer state. in the transfer state, when 8 or 16 transfer clock cycles are input, or if an smr1 dummy read is executed, the octal/hexadecimal counter is reset to h'0, and sci1 enters the serial clock pending state. writing to smr1 in the transfer state will reset the octal/hexadecimal counter to h'0 and change to the serial start pending state. in transitions from the transfer state to another state, the resetting of the octal/hexadecimal counter to h'0 sets bit irrs1 in irr3 to 1. if an internal clock source is selected, a dummy read of smr1 starts output of the serial clock, which stops after 8 or 16 clock output cycles. after writing to smr1 in the serial clock pending state or transfer state, it is necessary to write to smr1 again in order to initialize the initial state of the serial communication interface. writing to smr1 changes the state to the serial start pending state. 186 figure 10-3 sci1 state transitions 10.3.6 serial clock error detection in the transfer state, if an extraneous pulse is superimposed on the normal serial clock signal due to external noise, sci1 may function incorrectly. serial clock errors can be detected by means of the procedure shown in figure 10-4. in the transfer clock pending state, if more than the normal 8 or 16 serial clock cycles are mistakenly input, sci1 changes from the transfer state to the transfer clock pending state and then back to the transfer state. after bit irrs1 in interrupt request register 3 (irr3) is cleared to 0, writing a value in serial mode register 1 (smr1) changes the state to serial start pending, and bit irrs1 is again set to 1. serial clock pending state octal counter = 000 or hexadecimal counter = 0000 transfer state octal counter / 000 or hexadecimal counter / 0000 smr1 write smr1 write (irrs1 1) smr1 dummy read (serial start) 8 or 16 serial clock cycles (internal clock) (irrs1 1) serial clock smr1 dummy read (serial start) (irrs1 1) 8 or 16 serial clock cycles (external clock) = = serial start (smr1 dummy read) pending state octal counter = 000 or hexadecimal counter = 0000 serial clock disabled. 187 figure 10-4 procedure for detecting serial clock errors 10.3.7 interrupts sci1 can generate interrupts for completion of transfer and for transmit/receive errors. these interrupts are assigned to the same vector address. when an sci1 transfer is complete, or when a transmit/receive error occurs before the transfer is complete, bit irrs1 in interrupt request register 3 (irr3) is set to 1. sci1 interrupt requests can be enabled or disabled in bit iens1 of interrupt enable register 3 (ienr3). for further details, see 3.2.2, interrupts. disable interrupts irrs1 0 smr1 write irrs1 = 1? normal completion serial clock error processing yes no transfer complete (irrs1 1) 188 section 11 sci2 11.1 overview serial communication interface 2 (sci2) has a 32-byte data buffer, for synchronous serial transfer of up to 32 bytes of data in one operation. 11.1.1 features sci2 features are as follows. automatic transfer of up to 32 bytes of data choice of internal clock sources ( f /8, f /4, f /2) or an external clock interrupts requested at completion of transfer or when error occurs 11.1.2 block diagram figure 11-1 shows a block diagram of sci2. figure 11-1 block diagram of sci2 f prescaler s (13 bits) shift clock generator circuit scr2 address decoder and r/w controller data buffer (32 bytes) bit counter star byte counter comparator circuit edar shift register internal data bus sck irrs2 so si /cs 2 2 notation: star: edar: irrs2: 2 start address register end address register serial communication interface 2 interrupt request flag (interrupt request register 3) 189 11.1.3 pin configuration table 11-1 shows the sci2 pin configuration. table 11-1 pin configuration name abbrev. i/o function sci2 clock pin sck 2 i/o sci2 clock input/output sci2 data input pin si 2 input sci2 receive data input sci2 data output pin so 2 output sci2 transmit data output sci2 chip select output pin cs output sci2 chip select output note: functions of pins p9 4 /sck 2 , p9 5 /si 2 / cs , and p9 6 /so 2 are switched in port mode register 2 (pmr2) and port mode register 3 (pmr3). for pmr2, see 7.10.2 1, port mode register 2 (pmr2). 11.1.4 register configuration table 11-2 shows the sci2 register configuration. table 11-2 sci2 registers name abbrev. r/w initial value address 32-byte data buffer r/w not fixed h'ff80 to h'ff9f start address register star r/w h'e0 h'ffa0 end address register edar r/w h'e0 h'ffa1 serial control register 2 scr2 r/w h'e0 h'ffa2 status register stsr r/w h'e0/h'e8 h'ffa3 port mode register 2 pmr2 r/w h'00 h'ffec port mode register 3 pmr3 r/w h'97 h'ffed 190 11.2 register descriptions 11.2.1 start address register (star) star is an 8-bit read/write register, for designating the transfer start address in the memory area from h'ff80 to h'ff9f allocated to the 32-byte data buffer. the 32 bytes from h'00 to h'1f designated by the lower 5 bits of star (bits sta4 to sta0) correspond to addresses h'ff80 to h'ff9f. data is sent or received continuously using the area defined in star and in the end address register (edar). bits 7 to 5 are reserved; they always read 1, and cannot be modified. upon reset, star is initialized to h'e0. 11.2.2 end address register (edar) edar is an 8-bit read/write register, for designating the transfer end address in the memory area from h'ff80 to h'ff9f allocated to the 32-byte data buffer. the 32 bytes from h'00 to h'1f designated by the lower 5 bits of edar (bits eda4 to eda0) correspond to addresses h'ff80 to h'ff9f. data is sent or received continuously using the area defined in star and edar. if the same value is designated in both star and edar, only one byte of data is transferred. bits 7 to 5 are reserved; they always read 1, and cannot be modified. upon reset, edar is initialized to h'e0. bit initial value read/write 7 1 6 1 5 1 4 sta4 0 r/w 3 sta3 0 r/w 0 sta0 0 r/w 2 sta2 0 r/w 1 sta1 0 r/w bit initial value read/write 7 1 6 1 5 1 4 eda4 0 r/w 3 eda3 0 r/w 0 eda0 0 r/w 2 eda2 0 r/w 1 eda1 0 r/w 191 11.2.3 serial control register 2 (scr2) scr2 is an 8-bit read/write register, for selecting whether sci2 transmits or receives, for gap insertion during continuous transfer, and for serial clock selection. upon reset, scr2 is initialized to h'e0. bits 7 to 5: reserved bits bits 7 to 5 are reserved; they always read 1, and cannot be modified. bit 4: transmit/receive select (i/o) bit 4 selects sci2 transmit or receive mode. bit 4 i/o description 0 sci2 is in receive mode. (initial value) 1 sci2 is in transmit mode. bits 3 and 2: gap select (gap2 to gap1) when data is transmitted or received continuously, gaps can be inserted at data divisions by holding the serial clock high for a length of time designated by bits 3 and 2. bits 3 and 2 are valid when an internal clock source is selected as the serial clock (ps1 and 0 11). data divisions may be placed every 8 bits or 16 bits; this is selected in bit git in the status register (stsr). bit 3 bit 2 gap2 gap1 description 0 0 serial clock keeps the same duty cycle even at data divisions. (initial value) 0 1 serial clock high level extended by one clock cycle at data divisions. 1 0 serial clock high level extended by two clock cycles at data divisions. 1 1 serial clock high level extended by eight clock cycles at data divisions. bit initial value read/write 7 1 6 1 5 1 4 i/o 0 r/w 3 gap2 0 r/w 0 ps0 0 r/w 2 gap1 0 r/w 1 ps1 0 r/w 192 bits 1 and 0: serial clock select (ps1 to ps0) bits 1 and 0 select one of three internal clock sources or an external clock. serial clock period ps1 ps0 pin sck 2 clock source f = 4 mhz f = 2 mhz f = 1 mhz 0 0 sck 2 output prescaler s f /2 (initial value) * 1 ? 2 ? 0 1 sck 2 output prescaler s f /4 1 ? 2 ? 4 ? 1 0 sck 2 output prescaler s f /8 2 ? 4 ? 8 ? 1 1 sck 2 input external clock note: * can be set, but operation is not guaranteed. 11.2.4 status register (stsr) notes: 1. not fixed 2. cleared to 0 by write operation to stsr. stsr is an 8-bit register indicating the sci2 operation state, error status, etc. writing to this register during data transmission may cause misoperation. upon reset, stsr is initialized to h'e0 or h'e8. bits 7 to 5: reserved bits bits 7 to 5 are reserved; they always read 1, and cannot be modified. bit 4: extended data bit (so2 last bit) bit 4 holds the last bit of transmitted data after transmission ends. output from pin so 2 can be altered by software by modifying this bit either before or after transmission. writing to this bit during data transmission may cause misoperation. bit 1 bit 2 prescaler ps1 ps0 divider ratio bit initial value read/write 7 1 6 1 5 1 4 0 r/w 3 ovr r/w * 2 0 stf 0 r/w 2 wt 0 r/w * 2 1 git 0 r/w so2 last bit * 1 193 bit 4 so2 last bit description 0 output from pin so 2 is low. (initial value) 1 output from pin so 2 is high. bit 3: overrun flag (ovr) if the amount of data transferred exceeds the buffer size setting, or if an extraneous pulse is superimposed on the normal serial clock due to external noise, sci2 overruns and bit 3 is set to 1. bit 3 ovr description 0 [clear conditions] when stsr is written to. (initial value) 1 [set conditions] when overrun occurs. bit 2: waiting flag (wt) if an attempt is made to execute a read or write instruction to the 32-byte buffer during a serial data transfer, the instruction is ignored, and bit 2 is set to 1 along with bit irrs2 in interrupt request register 3 (irr3). bit 2 wt description 0 [clear conditions] when stsr is written to. (initial value) 1 [set conditions] when a read/write to the 32-byte buffer is attempted during serial transfer. bit 1: gap interval flag (git) bit 1 designates whether the extended serial clock high-level interval designated in bits gap2 and gap1 in serial control register 2 (scr2) occurs every 8 bits or every 16 bits. this setting is valid only for internal clock operation. bit 1 git description 0 gap specified by gap2 and gap1 is inserted every 16 bits. (initial value) 1 gap specified by gap2 and gap1 is inserted every 8 bits. 194 bit 0: start/busy flag (stf) setting bit 0 to 1 starts an sci2 transfer operation. this bit stays at 1 during the transfer, and is cleared to 0 after the transfer is complete. it can therefore be used as a busy flag as well. clearing this bit to 0 during a transfer aborts the transfer, initializing sci2. the contents of the 32-byte data buffer and of registers other than stsr are unchanged when this happens. bit 0 stf explanation 0 [read access] (initial value) indicates transfer not in progress. [write access] stops transfer. 1 [read access] indicates transfer in progress. [write access] starts transfer. 11.2.5 port mode register 3 (pmr3) pmr3 is an 8-bit read/write register, for enabling the pmos transistors of sci1 and sci2 data output pins (pin p9 3 /so 1 and pin p9 6 /so 2 ), and for controlling sci2 chip select output (pin si 2 / cs ). upon reset, pmr3 is initialized to h'97. for bit 3, see 10.2.6, port mode register 3 (pmr3). bit 7: reserved bit bit 7 is reserved; it always reads 1, and cannot be modified. bit initial value read/write 7 1 6 0 r/w 5 cs 0 r/w 4 1 3 0 r/w 0 1 2 1 1 1 so2 pmos so1 pmos 195 bit 6: pin so 2 pmos on/off (so2pmos) bit 6 enables or disables the pmos buffer transistor of pin p9 6 /so 2 . bit 6 so2pmos description 0 pmos transistor of pin p9 6 /so 2 is enabled: cmos output. (initial value) 1 pmos transistor of pin p9 6 /so 2 is disabled: nmos open-drain output. bit 5: chip select output select (cs) in combination with bit si2 in port mode register 2 (pmr2), bit 5 selects the cs output function of pin p9 5 /si 2 / cs . the cs output pin function is valid when an internal clock source is selected as the serial clock, and only in transmit mode. pmr2 pmr3 bit 5 bit 5 si2 cs description 0 0 pin p9 5 /si 2 / cs functions as p9 5 i/o pin. (initial value) 1 pin p9 5 /si 2 / cs functions as p9 5 i/o pin. 1 0 pin p9 5 /si 2 / cs functions as si 2 input pin. 1 pin p9 5 /si 2 / cs functions as cs output pin. bits 4 and 2 to 0: reserved bits these bits are reserved; they always read 1, and cannot be modified. 196 11.3 operation 11.3.1 overview sci2 has a 32-byte data buffer, making possible continuous transfer of up to 32 bytes of data with one operation. sci2 transmits and receives data in synchronization with clock pulses. selection of transmit or receive mode and of the serial clock is made in serial control register 2 (scr2). the start address register (star) and end address register (edar) designate the area within the 32-byte data buffer for holding transfer data. the address range from h'ff80 to h'ff9f is allocated to this data buffer. the start and end positions of the transfer data area are indicated in the lower 5 bits of star and edar. after parameters have been set in port mode register 2 (pmr2), port mode register 3 (pmr3), scr2, star, and edar, then when the stf bit of the status register (stsr) is set to 1, sci2 begins a transfer operation. stf remains set to 1 during the transfer, and is cleared to 0 when the transfer is complete. the stf bit can therefore be used as a busy flag. clearing the stf bit to 0 during a transfer stops the transfer operation and initializes sci2. the contents of the data buffer and of other registers are unchanged in this case. during a transfer, the cpu cannot read or write the data buffer. if a write instruction is issued it is ignored; it has the same effect as a nop instruction except that it takes more states. read access during a transfer yields h'ff. when the transfer is complete, or if a data buffer read or write is attempted during the transfer, bit irrs2 in interrupt request register 3 (irr3) is set to 1. in case of an overrun error or a data buffer read or write during the transfer, bit ovr or wt of stsr is set to 1. note: if the start address is set to a value higher than the end address, the result is as shown in figure 11-2. the data transfer wraps around from address h'ff9f to address h'ff80 and continues to the end address. 197 figure 11-2 operation when start address exceeds end address 11.3.2 clock three internal clock sources or an external clock may be selected as the serial clock. when an internal clock is selected, pin sck 2 becomes the clock output pin. 11.3.3 data transfer format figure 11-3 shows the sci2 data transfer format. data is sent and received starting from the least significant bit, in lsb-first format. transmit data is output from one falling edge of the serial clock until the next falling edge. receive data is latched at the rising edge of the clock. when sci2 operates on an internal clock and is in transmit mode, a gap may be inserted at data divisions (every 8 bits or 16 bits). during this gap, the serial clock stays at the high level for a designated number of clock cycles (see figures 11-4 through 11-6). the cs output remains low during the gap. gap insertion and the length of the gap are designated in bits gap2 and gap1 in serial control register 2 (scr2). bit git in the status register (stsr) designates whether gaps occur at 8-bit or 16-bit intervals. h'ff80 h'ff9f h'00 h'1f end address start address end start 198 figure 11-3 synchronous data transfer format figure 11-4 1-clock gap insertion (bits gap2 and gap1 = 01) figure 11-5 2-clock gap insertion (bits gap2 and gap1 = 10) sck output so si input data latch timing 2 2 2 does not go to low level bit 14 (bit 6) bit 15 (bit 7) * bit 16 (bit 8) bit 17 (bit 9) note: * when bit git = 1, a gap is inserted at 8-bit intervals. sck output so si input data latch timing 2 2 2 does not go to low level bit 14 (bit 6) bit 15 (bit 7) * bit 16 (bit 8) note: * when bit git = 1, a gap is inserted at 8-bit intervals. cs sck 2 so 2 don? care held bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 199 figure 11-6 8-clock gap insertion (bits gap2 and gap1 = 11) 11.3.4 data transmit/receive 1. sci2 initialization serial communication on sci2 first of all requires that sci2 be initialized by software. this involves clearing bit stf in the status register (stsr) to 0, then selecting pin functions and transfer modes in port mode register 2 (pmr2), port mode register 3 (pmr3), the start address register (star), the end address register (edar), and serial control register 2 (scr2). 2. transmitting a transmit operation is carried out as follows. set bit so2 in port mode register 2 (pmr2) to 1, making pin p9 6 /so 2 the so 2 output pin. if necessary, set the so2pmos bit and cs bit in pmr3 for nmos open-drain output at pin so 2 and for chip select output at pin p9 5 /si 2 / cs . write transmit data in the 32-byte data buffer (h'ff80 to h'ff9f). set the transfer start address in the lower 5 bits of star. set the transfer end address in the lower 5 bits of edar. in scr2, select transmit mode (bit i/o = 1), the serial clock, and gap insertion (internal clock operation only). select the data gap interval with bit git of strs, then set bit stf to 1. setting bit stf starts the transmit operation. sck output so si input data latch timing 2 2 2 bit 14 (bit 6) bit 15 (bit 7) * bit 16 (bit 8) note: * when bit git = 1, a gap is inserted at 8-bit intervals. serial clock 8 200 after data transmission is complete, bit irrs2 in interrupt request register 3 (irr3) is set to 1, and bit stf in stsr is cleared to 0. if an internal clock source is used, a serial clock is output from pin sck 2 in synchronization with the transmit data. after data transmission is completed, the serial clock is not output until bit stf is again set. during this time, pin so2 continues to output the value of the last bit transmitted. when an external clock source is used, data is transmitted in synchronization with the serial clock input at pin sck 2 . after data transmission is completed, further transmission does not take place even if the serial clock continues to be input; pin so 2 continues to output the value of the last bit transmitted. between transmissions, the output value of pin so 2 can be changed by rewriting bit so2 last bit in stsr. an attempt to read or write the data buffer during transmission will cause bit irrs2 in irr3 to be set to 1. bit wt in stsr will also be set to 1. 3. receiving a receive operation is carried out as follows. set bit si2 in port mode register 2 (pmr2) to 1, making pin p9 5 /si 1 /cs the si 2 input pin. allocate an area to hold the received data in the 32-byte data buffer and set the start address in the lower 5 bits of the start address register (star). set the transfer end address in the lower 5 bits of the end address register (edar). in serial control register 2 (scr2), select receive mode (bit i/o = 0) and the serial clock. set bit stf of the status register (stsr) to 1, starting the receive operation. after receiving is completed, bit irrs2 in interrupt request register 3 (irr3) is set to 1, and bit stf is cleared to 0. read the received data from the data buffer. if an internal clock source is used, setting bit stf to 1 in stsr immediately starts a data receive operation. the serial clock is output from pin sck 2 . 201 when an external clock source is used, after bit stf is set, data is received in synchronization with the clock input at pin sck 2 . after receiving is completed, no further receive operations take place until bit stf is again set, even if the serial clock continues to be input. an attempt to read or write the data buffer during receiving will cause bit irrs2 in irr3 and bit wt in stsr to be set to 1. bit ovr in stsr is set to 1 if an overrun error occurs. when sci2 operates on an internal clock and is in transmit mode, a gap may be inserted at data divisions (every 8 bits or 16 bits). during this gap, serial clock stays at the high level for a designated number of clock cycles (see figures 11-4 through 11-6). gap insertion and the length of the gap are designated in bits gap2 and gap1 of scr2. bit git of stsr designates whether gaps occur at 8-bit or 16-bit intervals. 11.4 interrupts sci2 can generate interrupts when a transfer is completed and when the data buffer is read or written during a transfer. these interrupts are assigned to the same vector address. when the above conditions occur, bit irrs2 in interrupt request register 3 (irr3) is set to 1. sci2 interrupt requests can be enabled or disabled in bit iens2 of interrupt enable register 3 (ienr3). for further details, see 3.2.2, interrupts. when an overrun error occurs, or when a read or write of the data buffer is attempted during a transfer, the ovr or wt bit in the status register (stsr) is set to 1. these bits can be used to determine the cause of the error. 11.5 application notes 1. do not write to any register during a transfer (while bit stf of stsr is set to 1), since this can cause misoperation. 2. when receiving, set bit si2 in port mode register 2 (pmr2) to 1 and clear bit cs in port mode register 3 (pmr3) to 0 to select the si 2 pin function. if bit cs = 1 and bit si2 = 1, selecting the cs pin function, incorrect data will be received. 202 section 12 vfd controller/driver 12.1 overview the h8/3714 series is equipped with an on-chip vacuum fluorescent display (vfd) controller/ driver and high-voltage, high-current pins, for direct vfd driving. 12.1.1 features the vfd controller/driver has the following features. maximum of 24 segment pins and 16 digit pins (20 segment pins, eight digit pins, and eight switched segment/digit pins). brightness can be adjusted in eight steps (dimmer function). automatic shifting of displayed digit. digit pins and segment pins can be switched over to use as general-purpose high-voltage pins. optional key scan interval. interrupt generated when key scan interval starts. 12.1.2 block diagram figure 12-1 shows a block diagram of the vfd controller/driver. figure 12-1 block diagram of vfd controller/driver internal data bus vfdr dbr vfsr irrks display timing generator circuit vfd display ram digit pins segment pins notation: vfdr: vfd digit control register dbr: digit beginning register vfsr: vfd segment control register irrks: key scan interrupt request flag (bit 6 of interrupt request register 3) 203 12.1.3 pin configuration table 12-1 shows the vfd controller/driver pin configuration. table 12-1 pin configuration name abbrev. i/o function digit/segment pins fd 0 /fs 7 to fd 7 /fs 0 output digit or segment pins for vacuum fluorescent display (function selected in dbr for each bit) digit pins fd 8 to fd 15 output digit pins for vacuum fluorescent display segment pins fs 8 to fs 23 output segment pins for vacuum fluorescent display 12.1.4 register configuration table 12-2 shows the vfd controller/driver register configuration. table 12-2 register configuration name abbrev. r/w initial value address vfd display ram r/w not fixed h'fec0 to h'feff vfd segment control register vfsr r/w h'20 h'ffb9 vfd digit control register vfdr r/w h'00 h'ffba digit beginning register dbr r/w h'20 h'ffbb 204 12.2 register descriptions 12.2.1 vfd digit control register (vfdr) vfdr is an 8-bit read/write register for control of digit output. upon reset, vfdr is initialized to h'00. bit 7: vfd mode bit (flmo) bit 7 designates the time per digit (t digit ) and the dimmer resolution (t dimmer ). t digit is also the time per key scan. digit/key scan time (t digit ) dimmer resolution (t dimmer ) period f = 4 mhz f = 2 mhz period f = 4 mhz f = 2 mhz 0 1536/ f 384 ? 768 ? 96/ f 24 ? 48 ? (initial value) (initial value) 1 768/ f 192 ? 384 ? 48/ f 12 ? 24 ? the frame period (t frame ) is calculated using the equation below. t frame = t digit (d + k) d: number of digit pins used k: 1 if key scan is used; 0 if not used bit initial value read/write 7 flmo 0 r/w 6 dm2 0 r/w 5 dm1 0 r/w 4 dm0 0 r/w 3 dr3 0 r/w 0 dr0 0 r/w 2 dr2 0 r/w 1 dr1 0 r/w bit 7 flmo 205 bits 6 to 4: digit waveform select (dm2 to dm0) bits 6 to 4 select the digit waveform. notes: 1. segment signal transition timing 2. for t dimmer and t digit , see under flmo bit. bit 6 dm2 bit 5 dm1 bit 4 dm0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 (initial value) t digit * 2 * 1 * 1 t dimmer * 2 digit signal waveform 206 bits 3 to 0: digit pin select (dr3 to dr0) bits 3 to 0, in combination with bits 3 to 0 of the digit beginning register (dbr), designate the digit pins used. bit 3 bit 2 bit 1 bit 0 dr3 dr2 dr1 dr0 pins valid as digit pins 0000fd 0 to fd 15 (initial value) 0001fd 0 to fd 14 0010fd 0 to fd 13 0011fd 0 to fd 12 0100fd 0 to fd 11 0101fd 0 to fd 10 0110fd 0 to fd 9 0111fd 0 to fd 8 1000fd 0 to fd 7 1001fd 0 to fd 6 1010fd 0 to fd 5 1011fd 0 to fd 4 1100fd 0 to fd 3 1101fd 0 to fd 2 1110fd 0 to fd 1 1111fd 0 note: for the switching between digit and segment use of pins fd 0 /fs 7 to fd 7 /fs 0 , which can function as either digit or segment pins, see 12.2.3, digit beginning register (dbr). figure 12-2 order of digit output fd m fd m+1 fd m+2 to fd n? fd n? fd n segment data 207 12.2.2 vfd segment control register (vfsr) vfsr is an 8-bit read/write register for control of segment output. upon reset, vfsr is initialized to h'20. bit 7: vfd/port switching flag (vflag) bit 7 designates whether pins pnn/fdnn and pnn/fsnn are used as vfd pins (fdnn, fsnn) or as general-purpose ports (pnn). bit 7 vflag description 0 all of pins pnn/fdnn and all of pins pnn/fsnn function as (initial value) general-purpose ports. 1 pnn/fdnn and pnn/fsnn function as vfd pins according to the designations in bits dr3 to dr0 in the vfd digit control register (vfdr), bits sr4 to sr0 in vfsr, and bits dbr3 to dbr0 in the digit beginning register (dbr). note: even when this flag is set to 1, during a key scan interval the segment pins function as general-purpose ports; for this reason, when this flag is read during a key scan interval it reads 0. bit 6: key scan enable (kse) bit 6 enables or disables the addition of a key scan interval (t digit ) to the vfd operation frame specified by the combination of bits dr3 to dr0 in the vfd digit control register, bits sr4 to sr0 in the vfd segment control register, and bits dbr3 to dbr0 in the digit beginning register. bit 6 kse description 0 no key scan interval. (initial value) 1 a key scan interval can be added. see also under bit 7 (vflag) above. bit 5: reserved bit bit 5 is reserved; it always reads 1, and cannot be modified. bit initial value read/write 7 vflag 0 r/w 6 kse 0 r/w 5 1 4 sr4 0 r/w 3 sr3 0 r/w 0 sr0 0 r/w 2 sr2 0 r/w 1 sr1 0 r/w 208 bits 4 to 0: segment pin select (sr4 to sr0) bits 4 to 0, in combination with bits 3 to 0 of the digit beginning register (dbr), designate the segment pins used. bit4 bit 3 bit 2 bit 1 bit 0 sr4 sr3 sr2 sr1 sr0 pins valid as segment pins 00000fs 0 (initial value) 00001fs 0 to fs 1 00010fs 0 to fs 2 00011fs 0 to fs 3 00100fs 0 to fs 4 00101fs 0 to fs 5 00110fs 0 to fs 6 00111fs 0 to fs 7 01000fs 0 to fs 8 01001fs 0 to fs 9 01010fs 0 to fs 10 01011fs 0 to fs 11 01100fs 0 to fs 12 01101fs 0 to fs 13 01110fs 0 to fs 14 01111fs 0 to fs 15 10000fs 0 to fs 16 10001fs 0 to fs 17 10010fs 0 to fs 18 10011fs 0 to fs 19 10100fs 0 to fs 20 10101fs 0 to fs 21 10110fs 0 to fs 22 10111fs 0 to fs 23 11000 11001 11010 11011 11100 11101 11110 11111 note: for the switching between digit and segment use of pins fd 0 /fs 7 to fd 7 /fs 0 , which can function as either digit or segment pins, see 12.2.3, digit beginning register (dbr). 209 12.2.3 digit beginning register (dbr) dbr is an 8-bit read/write register for on/off control of the vfd controller/driver and for switching functions of pins that can be either digit or segment pins. bit 7: vfd enable (vfde) bit 7 switches the vfd controller/driver on and off. bit 7 vfde description 0 vfd controller/driver is in reset state. (initial value) 1 vfd controller/driver is operative. note: this setting is unrelated to whether pins pnn/fdnn and pnn/fsnn are used as vfd pins or as general-purpose ports. bit 6: display bit (disp) bit 6 switches the display on and off. bit 6 disp description 0 all segment pins (fs) are in the non-illuminating state (pulled down). (initial value) register and ram values are unchanged. digit pins (fd) continue operating. 1 display ram data is output to segment pins (fs). bit 5: reserved bit bit 5 is reserved; it always reads 1, and cannot be modified. bit 4: reserved bit bit 4 is reserved, but it can be written and read. bit initial value read/write 7 vfde 0 r/w 6 disp 0 r/w 5 1 4 0 r/w 3 dbr3 0 r/w 0 dbr0 0 r/w 2 dbr2 0 r/w 1 dbr1 0 r/w 210 bits 3 to 0: digit/segment pin function switch (dbr3 to dbr0) bits 3 to 0 designate the first digit pin and the first segment pin of those pins that can function both ways. bits dr3 to dr0 of the vfd digit control register (vfdr) and bits sr4 to sr0 of vfsr must be set so that the first digit and segment pins are operational. otherwise these pins will not function. bit 3 bit 2 bit 1 bit 0 dbr3 dbr2 dbr1 dbr0 functions of fd 0 /fs 7 to fd 7 /fs 0 0000fd 0 to fd 7 (initial value) 0001fd 1 to fd 7 , fs 7 0010fd 2 to fd 7 , fs 7 to fs 6 0011fd 3 to fd 7 , fs 7 to fs 5 0100fd 4 to fd 7 , fs 7 to fs 4 0101fd 5 to fd 7 , fs 7 to fs 3 0110fd 6 to fd 7 , fs 7 to fs 2 0111 fd 7 , fs 7 to fs 1 1 *** fs 7 to fs 0 notes: digit pins (fd) and segment pins (fs) are controlled by both vfdr and vfsr. during a key scan interval, digit pins (fd) and segment pins (fs) function as general-purpose ports. * don? care. 211 12.3 operation 12.3.1 overview the vfd controller/driver may use up to 24 segment pins (fs) and up to 16 digit pins (fd). of these, 8 pins may be used as either segment or digit pins; their function is switched in the digit beginning register (dbr). the 32 pins assigned to the vfd controller are high-voltage, high- current pins capable of directly driving a vfd. 12.3.2 control section the control section consists of the vfd digit control register (vfdr), vfd segment control register (vfsr), digit beginning register (dbr), display timing generator circuit, and vfd display ram (see figure 12-1). display timing is determined by the number of digits per frame. when the key scan feature is activated, the frame is extended by one digit; during that interval only, segment pins and digit pins may be used as general purpose ports by the cpu. these pins are in the non-illuminating state (pulled down) during the key scan interval. 12.3.3 ram bit correspondence to digits/segments vfd display data is set in the vfd display ram at addresses h'fec0 through h'feff. table 12-3 shows the correspondence between digit/segment pins and the vfd display ram bits. 212 213 table 12-3 digit/segment pins and vfd display ram bits note: areas not used for display may be used as general-purpose ram. 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 2322212019181716 h'fec3 h'fec2 h'fec7 h'fec6 h'fecb h'feca h'fecf h'fece h'fed3 h'fed2 h'fed7 h'fed6 h'fedb h'feda h'fedf h'fede h'fee3 h'fee2 h'fee7 h'fee6 h'feeb h'feea h'feef h'feee h'fef3 h'fef2 h'fef7 h'fef6 h'fefb h'fefa h'feff h'fefe msb lsb msb lsb 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 1514131211109 8 76 543210 h'fec1 h'fec0 h'fec5 h'fec4 h'fec9 h'fec8 h'fecd h'fecc h'fed1 h'fed0 h'fed5 h'fed4 h'fed9 h'fed8 h'fedd h'fedc h'fee1 h'fee0 h'fee5 h'fee4 h'fee9 h'fee8 h'feed h'feec h'fef1 h'fef0 h'fef5 h'fef4 h'fef9 h'fef8 h'fefd h'fefc msb lsb msb lsb port seg dig 6 0 0 6 1 1 6 2 2 6 3 3 6 4 4 6 5 5 6 6 6 6 7 7 7 0 8 7 1 9 7 2 10 7 3 11 7 4 12 7 5 13 7 6 14 7 7 15 port seg dig 06 0 16 1 26 2 36 3 46 4 56 5 66 6 76 7 87 0 97 1 10 7 2 11 7 3 12 7 4 13 7 5 14 7 6 15 7 7 12.3.4 procedure for starting operation the procedure for starting operation of the vfd controller/driver is given below for a case in which digit pins fd 3 to fd 15 and segment pins fs 5 to fs 23 are used. it is assumed that data has already been written to the vfd display ram area. select the digit/key-scan time and dimmer resolution with bit flmo of the vfd digit control register (vfdr), and select the digit waveform with bits dm2 to dm0. clear bits dr3 to dr0 to 0000, making pins fd 0 to fd 15 operational. set the vflag bit of the vfd segment control register (vfsr) to 1, making the selected pins valid as vfd pins. set bit kse to enable or disable the key scan interval. set bits sr4 to sr0 to 11011, making pins fs 0 to fs 23 operational. set bits dbr3 to dbr0 in the digit beginning register (dbr) to 0011, designating pin fd 3 as the first digit pin and pin fs 5 as the first segment pin. set bit disp to 1, turning the display on, and set bit vfde to 1, starting vfd controller/driver operation. 12.4 interrupts when the key scan interval starts, bit irrks in interrupt request register 3 (irr3) is set to 1. these vfd interrupt requests can be enabled or disabled by means of bit ienks of interrupt enable register 3 (ienr3). for further details, see 3.2.2, interrupts. 12.5 occurrence of flicker when vfd registers are rewritten the vfd controller/driver is initialized whenever one of its registers (vfdr, vfsr, dbr) is rewritten. if this initialization takes place while a digit is being displayed, the contents displayed just prior to initialization will in some cases remain as an after-image in other digits. (this depends in part on the performance of the vacuum fluorescent display, but a momentary glow may be visible.) frequent rewriting of the registers can make these after-images bright enough to appear as a false display. this problem can be avoided by employing the following programming sequence when vfd controller/driver registers are rewritten. step description 1. disp = 0 2. vflag = 0 3. rewrite register (flmo, dm0 to dm3, etc.) 4. wait for at least t digit (display time of one digit). (execute other routines.) if the wait time is too long, the entire display may flicker. if the key scan feature is activated, this wait time does not have to be specially programmed. 5. vflag = 1 6. disp = 1 214 section 13 a/d converter 13.1 overview the h8/3714 series includes on-chip a resistance-ladder type successive-approximation a/d converter, which can convert up to eight channels of analog input. 13.1.1 features the a/d converter has the following features. 8-bit resolution eight input channels conversion time: 14.8 ? per channel (min, at f osc = 8.38 mhz) built-in sample-and-hold function interrupt requested on completion of a/d conversion 215 13.1.2 block diagram figure 13-1 shows a block diagram of the a/d converter. figure 13-1 block diagram of a/d converter p0 0 /an 0 port port port port port port port port mpx pmr0 (8b) amr (4b) p0 1 /an 1 p0 2 /an 2 p0 3 /an 3 p0 4 /an 4 p0 5 /an 5 p0 6 /an 6 p0 7 /an 7 reference voltage av cc av ss v ref r 1 r 255 r 254 r 253 r 252 r 251 + adsr control logic chopper-type comparator successive approximation finds the input voltage by changing a reference voltage (v ). ref reset lpm (low-power mode) interrupt internal data bus control circuitry (successive approximation, interrupt request, etc.) one of 256 switches is selected by binary search. the reference voltage value resulting from eight comparisons is set in addr. (the eighth value is equal to the analog input voltage.) the internal ladder resistance is 35 k to 40 k typ (approximately). upon reset and in low-power operation modes (sleep, watch, subactive, or standby modes), the ladder resistance is disconnected from av ww ss by a switching transistor. the av current at this time is a leakage current alcc of 1 a or less (approximate value). cc m notation: pmr0: amr: adsr: adrr: irrad: reset: lpm: port mode register 0 a/d mode register a/d start register a/d result register a/d conversion end interrupt request flag (interrupt request register 3) signal set to 1 upon reset signal set to 1 in low-power modes adrr 216 13.1.3 pin configuration table 13-1 shows the a/d converter pin configuration. table 13-1 pin configuration name abbrev. i/o function analog power supply pin av cc input analog power supply and reference voltage analog ground pin av ss input analog ground and reference voltage analog input pin 0 an 0 input analog input channel 0 analog input pin 1 an 1 input analog input channel 1 analog input pin 2 an 2 input analog input channel 2 analog input pin 3 an 3 input analog input channel 3 analog input pin 4 an 4 input analog input channel 4 analog input pin 5 an 5 input analog input channel 5 analog input pin 6 an 6 input analog input channel 6 analog input pin 7 an 7 input analog input channel 7 13.1.4 register configuration table 13-2 shows the a/d converter register configuration. table 13-2 register configuration name abbrev. r/w initial value address a/d mode register amr r/w h'78 h'ffbc a/d start register adsr r/w h'7f h'ffbe a/d result register adrr r not fixed h'ffbd port mode register 0 pmr0 w h'00 h'ffef 217 13.2 register descriptions 13.2.1 a/d result register (adrr) note: * not fixed the a/d result register (adrr) is an 8-bit read-only register for holding the result of analog-to- digital conversion. adrr can be read by the cpu at any time, but the adrr value during a/d conversion is not fixed. after a/d conversion is complete, the conversion result is stored in adrr as 8-bit data; this data is held in adrr until the next conversion operation starts. adrr is not cleared on reset. 13.2.2 a/d mode register (amr) amr is an 8-bit read/write register for selecting the a/d conversion speed and analog input pin. writing to amr should be done with the a/d start flag (adsf) cleared to 0 in the a/d start register (adsr). upon reset, amr is initialized to h'78. bit initial value read/write 7 adr7 r 6 adr6 r 5 adr5 r 4 adr4 r 3 adr3 r 0 adr0 r 2 adr2 r 1 adr1 r ***** * * * bit initial value read/write 7 amr7 0 r/w 6 1 5 1 4 1 3 1 0 amr0 0 r/w 2 amr2 0 r/w 1 amr1 0 r/w 218 bit 7: clock select (amr7) bit 7 sets the a/d conversion speed. *1 bit 7 amr7 conversion period * 2 f = 2 mhz f = 4 mhz 0 62/ f 31 ? 14.8 ? (initial value) 1 31/ f 15.5 ? * 1 notes: 1. operation is not guaranteed if the conversion time is less than 14.8 ?. set bit 7 for a value of at least 14.8 ?. 2. a/d conversion starts after a value of 1 is written to adsf. the conversion period starts when the start flag is set and ends when it is reset upon completion of conversion. the actual time during which sample and hold are repeated is called the conversion interval (see figure 13-2). figure 13-2 internal operation of a/d converter state conversion interval conversion period (31 or 62 states) interrupt request flag irq sampling (cpu) when conversion is complete, the start flag is reset and the interrupt request flag is set. an interrupt is recognized by the cpu in the last instruction execution state, and interrupt exception handling is executed after that instruction is completed. note: irq sampling: mov b. instruction execution write start flag 219 bits 6 to 3: reserved bits bits 6 to 3 are reserved; they always read 1, and cannot be modified. bits 2 to 0: channel select (amr2 to amr0) bits 2 to 0 select the analog input channel. settings are also required in port mode register 0 (pmr0). see 13.2.4, port mode register 0 (pmr0). bit 2 bit 1 bit 0 amr2 amr1 amr0 analog input channel 000 an 0 (initial value) 001 an 1 010 an 2 011 an 3 100 an 4 101 an 5 110 an 6 111 an 7 220 13.2.3 a/d start register (adsr) the a/d start register (adsr) is an 8-bit read/write register for starting and stopping a/d conversion. a/d conversion is started by writing 1 to the a/d start flag (adsf). when conversion is complete, the converted data is set in the a/d result register (adrr), and at the same time adsf is cleared to 0. bit 7: a/d start flag (adsf) bit 7 is for controlling and confirming the start and end of a/d conversion. bit 7 adsf description 0 [read access] (initial value) indicates that a/d conversion has been completed or stopped. [write access] stops a/d conversion. 1 [read access] indicates a/d conversion in progress. [write access] starts a/d conversion. bits 6 to 0: reserved bits bits 6 to 0 are reserved; they always read 1, and cannot be modified. bit initial value read/write 7 adsf 0 r/w 6 1 5 1 4 1 3 1 0 1 2 1 1 1 221 13.2.4 port mode register 0 (pmr0) pmr0 is an 8-bit write-only register for designating whether each of the port 0 pins is used as a general-purpose input pin or as an analog input channel to the a/d converter. designation is made separately for each pin. upon reset, pmr0 is initialized to h'00. bit n ann description 0 pin p0 n /an n is used for general-purpose input. (initial value) 1 pin p0 n /an n is an analog input channel. (n = 0 to 7) 13.3 operation the a/d converter operates by successive approximations, and yields its conversion result as 8-bit data. a/d conversion begins when software sets the a/d start flag (bit adsf) to 1. bit adsf keeps a value of 1 during a/d conversion, and is cleared to 0 automatically when conversion is complete. the completion of conversion also sets bit irrad in interrupt request register 3 (irr3) to 1. an a/d conversion end interrupt is requested if bit ienad in interrupt enable register 3 (ienr3) is set to 1. if the conversion time or input channel needs to be changed in the a/d mode register (amr) during a/d conversion, bit adsf should first be cleared to 0, stopping the conversion operation, in order to avoid misoperation. 13.4 interrupts when a/d conversion is complete (adsf changes from 1 to 0), bit irrad in interrupt request register 3 (irr3) is set to 1. a/d conversion end interrupts can be enabled or disabled by means of bit ienad in interrupt enable register 3 (ienr3). for further details see 3.2.2, interrupts. bit initial value read/write 7 an7 0 w 6 an6 0 w 5 an5 0 w 4 an4 0 w 3 an3 0 w 0 an0 0 w 2 an2 0 w 1 an1 0 w 222 13.5 typical use an example of how the a/d converter can be used is given below, using channel 1 (an 1 ) as the analog input channel. figure 13-3 shows the operation timing for this example. 1. bits amr2 to amr0 of the a/d mode register (amr) are set to 001, and bits an7 to an0 of port mode register 0 (pmr0) are set to 00000010, making an 1 the analog input channel. interrupt request is cleared by setting bit irrad to 0, a/d interrupts are enabled by setting bit ienad to 1, and a/d conversion is started by setting bit adsf to 1. 2. when a/d conversion is complete, bit irrad is set to 1, and the a/d conversion results are sent to the a/d result register (adrr). at the same time adsf is cleared to 0, and the a/d converter goes to the idle state. 3. bit ienad = 1, so an a/d conversion end interrupt is requested. 4. the a/d interrupt handling routine starts. 5. the a/d conversion result is read and processed. 6. the a/d interrupt handling routine ends. if adsf is set to 1 again afterward, a/d conversion starts and steps 2 through 6 take place. figures 13-4 and 13-5 show flow charts of procedures for using the a/d converter. 223 figure 13-3 typical a/d converter operation timing interrupt ienad adsf channel 1 (an ) operation states set * set * set * a/d conversion 1 a/d conversion 2 conversion result read a/d conversion result 1 conversion result read a/d conversion result 2 note: * ( ) indicates instruction execution by software. 1 a/d conversion starts adrr idle ** when the next a/d conversion starts, the previous result is lost. reset * idle idle 224 figure 13-4 flow chart of procedure for using a/d converter (1) (polling by software) set a/d conversion speed and input channels start disable a/d conversion end interrupt start a/d conversion read adsr adsf = 0? read adrr data perform a/d conversion? end yes no yes no 225 figure 13-5 flow chart of procedure for using a/d converter (2) (interrupts used) clear bit irrad to 0 in irr3 perform a/d conversion? end start a/d conversion end interrupt? read adrr data no yes no yes set a/d converter speed and input channels enable a/d conversion end interrupt start a/d conversion clear bit irrad to 0 226 13.6 application notes 1. data in the a/d result register (adrr) should be read only when the a/d start flag (adsf) in the a/d start register (adsr) is cleared to 0. 2. changing a digital input signal at a nearby pin during a/d conversion may adversely affect conversion accuracy. 3. the pin selected as an analog input channel in the a/d mode register (amr) must also be designated as an analog input channel in port mode register 0 (pmr0). 227 228 section 14 electrical specifications 14.1 absolute maximum ratings table 14-1 gives the absolute maximum ratings. table 14-1 absolute maximum ratings item symbol rating unit notes supply voltage v cc ?.3 to +7.0 v 1, 2 programming voltage v pp ?.3 to +14.0 v 1, 2, 3 analog supply voltage av cc ?.3 to +7.0 v 1, 2 analog input voltage av in ?.3 to av cc +0.3 v 1, 2 pin voltage (standard pins) v t ?.3 to v cc +0.3 v 1, 2, 4 pin voltage (high-voltage pins) v t v cc ?5 to v cc +0.3 v 1, 2, 5 operating temperature t op ?0 to +75 ? 1, 2 storage temperature t stg ?5 to +125 ? 1, 2 notes: 1. permanent damage may occur to the chip if maximum ratings are exceeded. normal operation should be under the conditions specified in electrical characteristics. exceeding these values can result in incorrect operation and reduced reliability. 2. all voltages are referenced to v ss . 3. applies to the ztat version. 4. applies to standard-voltage pins. 5. applies to high-voltage pins. 229 14.2 HD6473714 electrical characteristics 14.2.1 HD6473714 dc characteristics table 14-2 gives the allowable current values of the HD6473714. table 14-3 gives the dc characteristics. table 14-2 allowable output current values conditions: v cc = 4.0 to 5.5 v, v ss = 0.0 v, t a = ?0 to +75? item symbol rating unit notes allowable input current (sink) i o 2 ma 1, 2 allowable output current (source) ? o 2 ma 2, 3 allowable output current (source) ? o 20 ma 3, 4 total allowable input current (sink) i o 50 ma 5 total allowable output current (source) i o 150 ma 6 notes: 1. allowable input current means the maximum current that can flow from each i/o pin to v ss . 2. applies to standard-voltage pins. 3. allowable output current means the maximum current that can flow from v cc to each i/o pin. 4. applies to high-voltage pins. 5. total allowable input current means the sum of current that can flow at one time from all i/o pins to v ss . 6. total allowable output current means the sum of current that can flow from v cc to all i/o pins. 230 table 14-3 dc characteristics conditions: unless otherwise indicated, v cc = 4.0 to 5.5 v, v disp = v cc ?40 to v cc , v ss = 0.0 v, t a = ?0 to +75? rating item symbol test conditions min typ max unit notes input high v ih res 0.8 v cc ? cc +0.3 v voltage irq 0 , irq 1 , irq 4 , irq 5 v cc = 2.7 to 5.5 v 0.9 v cc ? cc +0.3 sck 1 , sck 2 incl. subactive mode si 1 , si 2 event , ud v cc = 2.7 to 5.5 v 0.7 v cc ? cc +0.3 v incl. subactive mode osc 1 v cc ?.5 v cc +0.3 v v cc = 2.7 to 5.5 v v cc ?.3 v cc +0.3 incl. subactive mode p0 0 to p0 7 v cc = 2.7 to 5.5 v 0.7 v cc ? cc +0.3 v p1 0 , p1 1 , incl. subactive mode p1 4 to p1 6 p9 0 to p9 7 p4 0 to p4 7 v cc = 2.7 to 5.5 v 0.7 v cc ? cc +0.3 v p5 0 to p5 7 incl. subactive mode p6 0 to p6 7 p7 0 to p7 7 p1 7 input low v il res , ?.3 0.2 v cc v voltage sck 1 , sck 2 irq 0 , irq 1 , v cc = 2.7 to 5.5 v ?.3 0.1 v cc irq 4 , irq 5 incl. subactive mode si 1 , si 2 event , ud v cc = 2.7 to 5.5 v ?.3 0.3 v cc v incl. subactive mode osc 1 ?.3 0.5 v v cc = 2.7 to 5.5 v ?.3 0.3 incl. subactive mode p0 0 to p0 7 v cc = 2.7 to 5.5 v ?.3 0.3 v cc v p1 0 , p1 1 , incl. subactive mode p1 4 to p1 6 p9 0 to p9 7 p4 0 to p4 7 v cc = 2.7 to 5.5 v v cc ?0 0.3 v cc v p5 0 to p5 7 incl. subactive mode p6 0 to p6 7 p7 0 to p7 7 p1 7 note: connect the test pin to v ss . applicable pins 231 table 14-3 dc characteristics (cont) conditions: unless otherwise indicated, v cc = 4.0 to 5.5 v, v disp = v cc ?40 to v cc , v ss = 0.0 v, t a = ?0 to +75? rating item symbol test conditions min typ max unit notes v oh ? oh = 1.0 ma v cc ?.0 v ? oh = 0.5 ma v cc ?.5 v cc = 2.7 to 5.5 v v cc ?.5 ? oh = 0.3 ma ? oh = 15 ma v cc ?.0 v ? oh = 10 ma v cc ?.0 ? oh = 4 ma v cc ?.0 v cc = 2.7 to 5.5 v v cc ?.0 v reference ? oh = 4 ma value output low v ol v cc = 4.0 to 5.5 v 0.4 v voltage i ol = 1.6 ma v cc = 2.7 to 5.5 v 0.4 v reference i ol = 0.5 ma value p4 0 to p4 7 pull-down v cc ?7 v p5 0 to p5 7 resistance p6 0 to p6 7 150 k w ; pull-down p7 0 to p7 7 voltage v cc ?0 v input |i il | res v in = 0.0 to v cc 40 a leakage current applicable pins p1 0 , p1 1 , p1 4 , p1 5 p9 0 to p9 7 pwm, so1, so 2 , sck 1 , sck 2 p1 0 , p1 1 , p1 4 , p1 5 p9 0 to p9 7 pwm, so 1 , so 2 , sck 1 , sck 2 output high voltage p4 0 to p4 7 p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 232 table 14-3 dc characteristics (cont) conditions: unless otherwise indicated, v cc = 4.0 to 5.5 v, v disp = v cc ?40 to v cc , v ss = 0.0 v, t a = ?0 to +75? rating item symbol test conditions min typ max unit notes i/o leakage |i il | test v in = 0.0 to v cc 1 a current sck 1 , sck 2 si 1 , si 2 irq 0 , irq 1 , irq 4 , irq 5 event , ud osc 1 p0 0 to p0 7 p1 0 , p1 1 p1 4 to p1 6 p9 0 to p9 7 p4 0 to p4 7 v in = v cc ?0 20 ? p5 0 to p5 7 to v cc p6 0 to p6 7 p7 0 to p7 7 p1 7 input c in input pins f = 1 mhz, v in = 0 v 20 pf capaci- other than t a = 25? tance power supply pins and i/o pins p1 6 / event 35 res 70 applicable pins 233 table 14-3 dc characteristics (cont) conditions: unless otherwise indicated, v cc = 4.0 to 5.5 v, v disp = v cc ?40 to v cc , v ss = 0.0 v, t a = ?0 to +75? rating item symbol test conditions min typ max unit notes i ope v cc v cc = 5 v, 17 ma f osc = 8 mhz v cc = 5 v, 9 f osc = 4 mhz v cc = 3 v, 6 f osc = 4 mhz i res v cc v cc = 5 v, 6 9 ma 1 f osc = 8 mhz v cc = 5 v, 3 5 f osc = 4 mhz v cc = 3 v, 1.5 f osc = 4 mhz i sleep v cc v cc = 5 v, 2.5 3.5 ma 1 f osc = 8 mhz v cc = 5 v, 1.5 2.0 f osc = 4 mhz v cc = 3 v, 1.0 f osc = 4 mhz i sub v cc v cc = 2.7 v 6 20 a 11 ? 2 16 ? reference value 22 ? 2 i watch v cc 3.2 6 a 3.8 a 2 10 ? reference value 12 ? 2 power i stby v cc 32 khz crystal 10 ? dissipation oscillator not used in standby x 1 = v cc mode applicable pins power dissipation when cpu operating in active mode power dissipation during reset in active mode reference value 1 power dissipation in sleep mode power dissipation in subactive mode power dissipation in watch mode v cc = 2.7 v 32 khz crystal oscillator used v cc = 5.0 v 32 khz crystal oscillator used v cc = 2.7 v 32 khz crystal oscillator used v cc = 5.0 v 32 khz crystal oscillator used 234 table 14-3 dc characteristics (cont) conditions: unless otherwise indicated, v cc = 4.0 to 5.5 v, v disp = v cc ?40 to v cc , v ss = 0.0 v, t a = ?0 to +75? rating item symbol test conditions min typ max unit notes ram data v stby v cc 32 khz crystal 2 v retention oscillator not used voltage in x 1 = v cc standby mode notes: 1. does not include current flowing to output buffer. 2. reference value when bypass capacitor of 47 ? is connected between v cc and v ss . applicable pins 235 14.2.2 HD6473714 ac characteristics table 14-4 gives the control signal timing of the HD6473714. table 14-5 gives the serial interface timing. table 14-4 control signal timing conditions: unless otherwise indicated, v cc = 4.0 to 5.5 v, v disp = v cc ?40 to v cc , v ss = 0.0 v, t a = ?0 to +75? rating item symbol test conditions min typ max unit f osc 2 8.4 mhz v cc = 2.7 to 5.5 v 2 4.2 clock cycle time t cyc 119 500 ns v cc = 2.7 to 5.5 v 238 500 f 238 1000 ns v cc = 2.7 to 5.5 v 476 1000 subclock pulse f x x 1 , x 2 v cc = 2.7 to 5.5 v 32.768 khz generator frequency subclock cycle t subcyc x 1 , x 2 v cc = 2.7 to 5.5 v 30.5 s time subactive f sub v cc = 2.7 to 5.5 v 244.14 s instruction cycle time t rc 40ms v cc = 2.7 to 5.5 v 60 t rc 20ms v cc = 2.7 to 5.5 v 40 oscillator t rc x 1 , x 2 v cc = 2.7 to 5.5 v 2 s settling time t cph osc 1 40 ns v cc = 2.7 to 5.5 v 100 t cpl osc 1 40 ns v cc = 2.7 to 5.5 v 100 t cpr osc 1 20ns v cc = 2.7 to 5.5 v 20 t cpf osc 1 20ns v cc = 2.7 to 5.5 v 20 applicable pins reference diagram figure 14-1 figure 14-1 clock pulse generator frequency instruction cycle time oscillator settling time (crystal oscillator) oscillator settling time (ceramic oscillator) external clock pulse width (high) external clock pulse width (low) external clock rise time external clock fall time osc 1 , osc 2 , osc 1 , osc 2 , osc 1 , osc 2 , osc 1 , osc 2 , 236 table 14-4 control signal timing (cont) conditions: unless otherwise indicated, v cc = 4.0 to 5.5 v, v disp = v cc ?40 to v cc , v ss = 0.0 v, t a = ?0 to +75? rating item symbol test conditions min typ max unit res pin pulse t rel res v cc = 2.7 to 5.5 v 10 f figure width (low) 14-2 irq pin pulse t ih irq 0 , irq 1 , v cc = 2.7 to 5.5 v 2 f figure width (high) irq 4 , irq 5 f sub 14-3 irq pin pulse t il irq 0 , irq 1 , v cc = 2.7 to 5.5 v 2 f width (low) irq 4 , irq 5 f sub event pin t evh event v cc = 2.7 to 5.5 v 2 f figure pulse width (high) 14-4 event pin t evl event v cc = 2.7 to 5.5 v 2 f pulse width (low) ud pin minimum t udh ud v cc = 2.7 to 5.5 v 2 f figure high/low width t udl 14-5 table 14-5 serial interface timing conditions: unless otherwise indicated, v cc = 4.0 to 5.5 v, v disp = v cc ?40 to v cc , v ss = 0.0 v, t a = ?0 to +75? rating item symbol test conditions min typ max unit output serial t scyc sck 1 , v cc = 2.7 to 5.5 v 2 f figure clock cycle time sck 2 14-6 output serial t sckh sck 1 ,v cc = 2.7 to 5.5 v 0.4 t scyc clock pulse width sck 2 (high) output serial t sckl sck 1 ,v cc = 2.7 to 5.5 v 0.4 t scyc clock pulse sck 2 width (low) t sckr 60ns v cc = 2.7 to 5.5 v 80 t sckf 60ns v cc = 2.7 to 5.5 v 80 input serial t scyc v cc = 2.7 to 5.5 v 1 f clock cycle time input serial t sckh v cc = 2.7 to 5.5 v 0.4 t scyc clock pulse width (high) applicable pins reference diagram output serial clock rise time output serial clock fall time sck 1 , sck 2 sck 1 , sck 2 sck 1 , sck 2 sck 1 , sck 2 applicable pins reference diagram 237 table 14-5 serial interface timing (cont) conditions: unless otherwise indicated, v cc = 4.0 to 5.5 v, v disp = v cc ?40 to v cc , v ss = 0.0 v, t a = ?0 to +75? rating item symbol test conditions min typ max unit input serial t sckl v cc = 2.7 to 5.5 v 0.4 t scyc figure clock pulse 14-6 width (low) t sckr 60ns v cc = 2.7 to 5.5 v 80 t sckf 60ns v cc = 2.7 to 5.5 v 80 t dso so 1 , so 2 200 ns v cc = 2.7 to 5.5 v 350 t ssi si 1 , si 2 230 ns v cc = 2.7 to 5.5 v 470 t hsi si 1 , si 2 230 ns v cc = 2.7 to 5.5 v 470 transfer pending t sck2 sck 2 when pin sck 2 is 0.2 40 s figure time input pin 14-7 when pin sck 2 is 0.4 40 input pin v cc = 2.7 to 5.5 v when pin sck 2 is 1 t scyc output pin v cc = 2.7 to 5.5 v transfer end t cs cs v cc = 2.7 to 5.5 v 3 4 f acknowledge time applicable pins reference diagram input serial clock rise time input serial clock fall time serial output data delay time serial input data setup time serial input data hold time sck 1 , sck 2 sck 1 , sck 2 sck 1 , sck 2 238 14.2.3 HD6473714 a/d converter characteristics table 14-6 gives the HD6473714 a/d converter characteristics. table 14-6 a/d converter characteristics conditions: unless otherwise indicated, v cc = 4.0 to 5.5 v, v disp = v cc ?40 to v cc , v ss = 0.0 v, t a = ?0 to +75? rating item symbol test conditions min typ max unit notes analog av cc av cc v cc ?.3 v cc v cc +0.3 v supply voltage analog av in an 0 to an 7 av ss ?v cc v input voltage ai cc av cc av cc = 5 v 200 ? ai stop reset and power- 10 ? down mode analog input c ain an 0 to an 7 30 pf capacitance allowable r ain an 0 to an 7 10k w signal source impedance resolution 8 bit absolute v cc = av cc = 5 v ?.5 lsb v cc = av cc = ?.5 reference 4.0 to 5.5 v value conversion 31 15.5 14.8 ? time applicable pins analog supply current absolute accuracy 239 14.3 hd6433712, hd6433713 and hd6433714 electrical characteristics 14.3.1 hd6433712, hd6433713 and hd6433714 dc characteristics table 14-7 gives the allowable current values of the hd6433712, hd6433713 and hd6433714. table 14-8 gives the dc characteristics. table 14-7 allowable output current values conditions: v cc = 4.0 to 5.5 v, v ss = 0.0 v, t a = ?0 to +75? item symbol rating unit notes allowable input current (sink) i o 2 ma 1, 2 allowable output current (source) ? o 2 ma 2, 3 allowable output current (source) ? o 20 ma 3, 4 total allowable input current (sink) i o 50 ma 5 total allowable output current (source) i o 150 ma 6 total allowable output current to v disp i o 30 ma 7 notes: 1. allowable input current means the maximum current that can flow from each i/o pin to v ss . 2. applies to standard-voltage pins. 3. allowable output current means the maximum current that can flow from v cc to each i/o pin. 4. applies to high-voltage pins. 5. total allowable input current means the sum of current that can flow at one time from all i/o pins to v ss . 6. total allowable output current means the sum of current that can flow from v cc to all i/o pins. 7. total allowable output current to v disp is the sum of current that can flow from all i/o pins to v disp . 240 table 14-8 dc characteristics conditions: unless otherwise indicated, v cc = 4.0 to 5.5 v, v disp = v cc ?40 to v cc , v ss = 0.0 v, t a = ?0 to +75? rating item symbol test conditions min typ max unit notes input high v ih res 0.8 v cc ? cc +0.3 v voltage irq 0 , irq 1 , irq 4 , irq 5 v cc = 2.5 to 5.5 v 0.9 v cc ? cc +0.3 sck 1 , sck 2 incl. subactive mode si 1 , si 2 event , ud v cc = 2.5 to 5.5 v 0.7 v cc ? cc +0.3 v incl. subactive mode osc 1 v cc ?.5 v cc +0.3 v v cc = 2.5 to 5.5 v v cc ?.3 v cc +0.3 incl. subactive mode p0 0 to p0 7 v cc = 2.5 to 5.5 v 0.7 v cc ? cc +0.3 v p1 0 , p1 1 incl. subactive mode p1 4 to p1 6 p9 0 to p9 7 p4 0 to p4 7 v cc = 2.5 to 5.5 v 0.7 v cc ? cc +0.3 v p5 0 to p5 7 incl. subactive mode p6 0 to p6 7 p7 0 to p7 7 p1 7 input low v il res , ?.3 0.2 v cc v voltage sck 1 , sck 2 irq 0 , irq 1 , v cc = 2.5 to 5.5 v ?.3 0.1 v cc irq 4 , irq 5 incl. subactive mode si 1 , si 2 event , ud v cc = 2.5 to 5.5 v ?.3 0.3 v cc v incl. subactive mode osc 1 ?.3 0.5 v v cc = 2.5 to 5.5 v ?.3 0.3 incl. subactive mode p0 0 to p0 7 v cc = 2.5 to 5.5 v ?.3 0.3 v cc v p1 0 , p1 1 incl. subactive mode p1 4 to p1 6 p9 0 to p9 7 p4 0 to p4 7 v cc = 2.5 to 5.5 v v cc ?0 0.3 v cc v p5 0 to p5 7 incl. subactive mode p6 0 to p6 7 p7 0 to p7 7 p1 7 note: connect the test pin to v ss . applicable pins 241 table 14-8 dc characteristics (cont) conditions: unless otherwise indicated, v cc = 4.0 to 5.5 v, v disp = v cc ?40 to v cc , v ss = 0.0 v, t a = ?0 to +75? rating item symbol test conditions min typ max unit notes v oh ? oh = 1.0 ma v cc ?.0 v ? oh = 0.5 ma v cc ?.5 v cc = 2.7 to 5.5 v v cc ?.5 ? oh = 0.3 ma ? oh = 15 ma v cc ?.0 v ? oh = 10 ma v cc ?.0 ? oh = 4 ma v cc ?.0 v cc = 2.7 to 5.5 v v cc ?.0 v reference ? oh = 4 ma value output low v ol p1 0 , p1 1 v cc = 4.0 to 5.5 v 0.4 v voltage p1 4 , p1 5 i ol = 1.6 ma p9 0 to p9 7 pwm, so 1 ,v cc = 2.7 to 5.5 v 0.4 v reference so 2 , sck 1 ,i ol = 0.5 ma value sck 2 v disp = v cc ?0 v v cc ?7 v with mos pull-down pull-down v cc ?7 resistance 150 k w ; pull-down voltage v cc ?0 v input |i il | res mask rom version: 1 a leakage v in = 0.0 to v cc current p1 0 , p1 1 p1 4 , p1 5 p9 0 to p9 7 pwm, so1, so 2 , sck 1 , sck 2 applicable pins output high voltage p4 0 to p4 7 p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p4 0 to p4 7 p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 242 table 14-8 dc characteristics (cont) conditions: unless otherwise indicated, v cc = 4.0 to 5.5 v, v disp = v cc ?40 to v cc , v ss = 0.0 v, t a = ?0 to +75? rating item symbol test conditions min typ max unit notes i/o leakage |i il | test v in = 0.0 to v cc 1 a current sck 1 , sck 2 si 1 , si 2 irq 0 , irq 1 irq 4 , irq 5 event , ud osc 1 p0 0 to p0 7 p1 0 , p1 1 p1 4 to p1 6 p9 0 to p9 7 p4 0 to p4 7 v in = v cc ?0 20 ? not p5 0 to p5 7 to v cc including p6 0 to p6 7 pins with p7 0 to p7 7 mos p1 7 pull-down ? p v cc = 5 v, v in = 0 v 50 300 ? v cc = 2.7 v, 25 reference v in = 0 v value i d v disp = v cc ?6 120 800 ? v in = v cc v disp = v cc ?8 280 reference v in = v cc value input c in input pins f = 1 mhz, v in = 0 v 15 pf capaci- other than t a = 25? tance power supply pins and i/o pins p1 7 30 applicable pins p1 0 , p1 1 p1 4 to p1 6 p9 0 to p9 7 p4 0 to p4 7 p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 pull-up mos current pull-down mos current 243 table 14-8 dc characteristics (cont) conditions: unless otherwise indicated, v cc = 4.0 to 5.5 v, v disp = v cc ?40 to v cc , v ss = 0.0 v, t a = ?0 to +75? rating item symbol test conditions min typ max unit notes i ope v cc v cc = 5 v, 15 ma f osc = 8 mhz v cc = 5 v, 8 f osc = 4 mhz v cc = 3 v, 5 f osc = 4 mhz i res v cc v cc = 5 v, 5 8 ma 1 f osc = 8 mhz v cc = 5 v, 2.5 4 f osc = 4 mhz v cc = 3 v, 1.3 f osc = 4 mhz i sleep v cc v cc = 5 v, 2 3 ma 1 f osc = 8 mhz v cc = 5 v, 1 1.5 f osc = 4 mhz v cc = 3 v, 0.6 f osc = 4 mhz i sub v cc ? 20 a ? a2 13 ? reference value 20 ? 2 i watch v cc 2.2 5 a 2.8 a 2 6 a reference value ? a2 power i stby v cc 32 khz crystal 5 a dissipation oscillator not used in standby x 1 = v cc mode applicable pins power dissipation when cpu operating in active mode power dissipation during reset in active mode reference value 1 power dissipation in sleep mode power dissipation in subactive mode power dissipation in watch mode v cc = 2.5 v 32 khz crystal oscillator used v cc = 5.0 v 32 khz crystal oscillator used v cc = 2.5 v 32 khz crystal oscillator used v cc = 5.0 v 32 khz crystal oscillator used 244 table 14-8 dc characteristics (cont) conditions: unless otherwise indicated, v cc = 4.0 to 5.5 v, v disp = v cc ?40 to v cc , v ss = 0.0 v, t a = ?0 to +75? rating item symbol test conditions min typ max unit notes ram data v stby v cc 32 khz crystal 2 v retention oscillator not used voltage in x 1 = v cc standby mode notes: 1. does not include current flowing to pull-up mos or output buffer. 2. reference value when bypass capacitor of 47 ? is connected between v cc and v ss . applicable pins 245 14.3.2 hd6433712, hd6433713 and hd6433714 ac characteristics table 14-9 gives the control signal timing of the hd6433712, hd6433713 and hd6433714. table 14-10 gives the serial interface timing. table 14-9 control signal timing conditions: unless otherwise indicated, v cc = 4.0 to 5.5 v, v disp = v cc ?40 to v cc , v ss = 0.0 v, t a = ?0 to +75? rating item symbol test conditions min typ max unit f osc 2 8.4 mhz v cc = 2.7 to 5.5 v 2 4.2 clock cycle time t cyc 119 500 ns v cc = 2.7 to 5.5 v 238 500 f 238 1000 ns v cc = 2.7 to 5.5 v 476 1000 subclock pulse f x x 1 , x 2 v cc = 2.5 to 5.5 v 32.768 khz generator frequency subclock cycle t subcyc x 1 , x 2 v cc = 2.5 to 5.5 v 30.5 s time subactive f sub v cc = 2.5 to 5.5 v 244.14 s instruction cycle time t rc 40ms v cc = 2.7 to 5.5 v 60 t rc 20ms v cc = 2.7 to 5.5 v 40 oscillator t rc x 1 , x 2 v cc = 2.7 to 5.5 v 2 s settling time t cph osc 1 40 ns v cc = 2.7 to 5.5 v 100 t cpl osc 1 40 ns v cc = 2.7 to 5.5 v 100 t cpr osc 1 20ns v cc = 2.7 to 5.5 v 20 t cpf osc 1 20ns v cc = 2.7 to 5.5 v 20 applicable pins reference diagram figure 14-1 figure 14-1 clock pulse generator frequency instruction cycle time oscillator settling time (crystal oscillator) oscillator settling time (ceramic oscillator) external clock pulse width (high) external clock pulse width (low) external clock rise time external clock fall time osc 1 , osc 2 , osc 1 , osc 2 , osc 1 , osc 2 , osc 1 , osc 2 , 246 table 14-9 control signal timing (cont) conditions: unless otherwise indicated, v cc = 4.0 to 5.5 v, v disp = v cc ?40 to v cc , v ss = 0.0 v, t a = ?0 to +75? rating item symbol test conditions min typ max unit res pin pulse t rel res v cc = 2.7 to 5.5 v 10 f figure width (low) 14-2 irq pin pulse t ih irq 0 , irq 1 v cc = 2.7 to 5.5 v 2 f figure width (high) irq 4 , irq 5 f sub 14-3 irq pin pulse t il irq 0 , irq 1 v cc = 2.7 to 5.5 v 2 f width (low) irq 4 , irq 5 f sub event pin t evh event v cc = 2.7 to 5.5 v 2 f figure pulse width (high) 14-4 event pin t evl event v cc = 2.7 to 5.5 v 2 f pulse width (low) ud pin minimum t udh ud v cc = 2.7 to 5.5 v 2 f figure high/low width t udl 14-5 table 14-10 serial interface timing conditions: unless otherwise indicated, v cc = 4.0 to 5.5 v, v disp = v cc ?40 to v cc , v ss = 0.0 v, t a = ?0 to +75? rating item symbol test conditions min typ max unit output serial t scyc sck 1 , v cc = 2.7 to 5.5 v 2 f figure clock cycle timing sck 2 14-6 output serial t sckh sck 1 ,v cc = 2.7 to 5.5 v 0.4 t scyc clock pulse width sck 2 (high) output serial t sckl sck 1 ,v cc = 2.7 to 5.5 v 0.4 t scyc clock pulse sck 2 width (low) t sckr 60ns v cc = 2.7 to 5.5 v 80 t sckf 60ns v cc = 2.7 to 5.5 v 80 input serial t scyc v cc = 2.7 to 5.5 v 1 f clock cycle timing input serial t sckh v cc = 2.7 to 5.5 v 0.4 t scyc clock pulse width (high) applicable pins reference diagram applicable pins reference diagram output serial clock rise time output serial clock fall time sck 1 , sck 2 sck 1 , sck 2 sck 1 , sck 2 sck 1 , sck 2 247 table 14-10 serial interface timing (cont) conditions: unless otherwise indicated, v cc = 4.0 to 5.5 v, v disp = v cc ?40 to v cc , v ss = 0.0 v, t a = ?0 to +75? rating item symbol test conditions min typ max unit input serial t sckl v cc = 2.7 to 5.5 v 0.4 t scyc figure clock pulse 14-6 width (low) t sckr 60ns v cc = 2.7 to 5.5 v 80 t sckf 60ns v cc = 2.7 to 5.5 v 80 t dso so 1 , so 2 200 ns v cc = 2.7 to 5.5 v 350 t ssi si 1 , si 2 230 ns v cc = 2.7 to 5.5 v 470 t hsi si 1 , si 2 230 ns v cc = 2.7 to 5.5 v 470 transfer pending t sck2 sck 2 when pin sck 2 is 0.2 40 s figure time input pin 14-7 when pin sck 2 is 0.4 40 input pin v cc = 2.7 to 5.5 v when pin sck 2 is 1 t scyc output pin v cc = 2.7 to 5.5 v transfer end t cs cs v cc = 2.7 to 5.5 v 3 4 f acknowledge time applicable pins reference diagram input serial clock rise time input serial clock fall time serial output data delay time serial input data setup time serial input data hold time sck 1 , sck 2 sck 1 , sck 2 sck 1 , sck 2 248 14.3.3 hd6433712, hd6433713 and hd6433714 a/d converter characteristics table 14-11 gives the hd6433712, hd6433713 and hd6433714 a/d converter characteristics. table 14-11 a/d converter characteristics conditions: unless otherwise indicated, v cc = 4.0 to 5.5 v, v disp = v cc ?40 to v cc , v ss = 0.0 v, t a = ?0 to +75? rating item symbol test conditions min typ max unit notes analog av cc av cc v cc ?.3 v cc v cc +0.3 v supply voltage analog av in an 0 to an 7 av ss ?v cc v input voltage ai cc av cc av cc = 5 v 200 ? ai stop reset and power- 10 ? down mode analog input c ain an 0 to an 7 30 pf capacitance allowable r ain an 0 to an 7 10k w signal source impedance resolution 8 bit v cc = av cc = 5 v ?.5 lsb v cc = av cc = ?.5 reference 4.0 to 5.5 v value conversion 31 15.5 14.8 ? time applicable pins analog supply current absolute accuracy 249 14.4 operational timing this section provides operational timing diagrams (figures 14-1 to 14-8). figure 14-1 system clock input timing figure 14-2 res pin pulse width (low) figure 14-3 irq pin input timing figure 14-4 event pin minimum pulse widths osc 1 v ih v il t cyc t cpr t cph t cpl t cpf f res v il t rel irq 0 , irq 1 , irq 4 , irq 5 v ih v il t il t ih event v ih v il t evl t evh 250 figure 14-5 ud pin minimum high/low width figure 14-6 sci i/o timing v ih v il t udl t udh ud v il or v ol * v ih or v oh * sck 1 sck 2 t scyc t sckf t sckl t sckh t dso t sckr v oh * v ol * t ssi t hsi so 1 so 2 si 1 si 2 output timing reference levels: output high level: output low level: note: * v oh : 2.0 v v ol : 0.8 v see figure 14-8 for the load conditions. 251 figure 14-7 serial communication interface 2 chip select timing figure 14-8 output load conditions v ol * t sck2 v oh * t cs cs sck 2 v il or v ol * v ih or v oh * output timing reference levels: output high level: output low level: note: * v oh : 2.0 v v ol : 0.8 v see figure 14-8 for the load conditions. output pin 30 pf 12 k w 2.4 k w v cc 252 14.5 differences in electrical characteristics between HD6473714 and hd6433712/hd6433713/hd6433714 table 14-12 shows the difference in electrical characteristics between the HD6473714 and hd6433712/hd6433713/hd6433714. table 14-12 differences in electrical characteristics between HD6473714 and hd6433712/hd6433713/hd6433714 mask rom version ztat version item symbol test conditions min typ max min typ max unit operation v cc 2.5 5.5 2.7 5.5 v range in subactive mode input leakage |i il | res 1 40 a current input c in p16/ event 15 35pf capacitance p17/v disp 30 20 res 15 70 i ope v cc v cc = 5 v, 15 17 ma f osc = 8 mhz v cc = 5 v, 8 9 f osc = 4 mhz v cc = 3 v, 5 6 f osc = 4 mhz i res v cc v cc = 5 v, 5 8 6 9 ma f osc = 8 mhz v cc = 5 v, 2.5 4 3 5 f osc = 4 mhz v cc = 3 v, 1.3 1.5 f osc = 4 mhz i sleep v cc v cc = 5 v, 2 3 2.5 3.5 f osc = 8 mhz v cc = 5 v, 1 1.5 1.5 2 f osc = 4 mhz v cc = 3 v, 0.6 1 f osc = 4 mhz applicable pins power dissipation when cpu operating in active mode power dissipation during reset in active mode power dissipation in sleep mode 253 table 14-12 differences in electrical characteristics between HD6473714 and hd6433713/hd6433714 (cont) mask rom version ztat version item symbol test conditions min typ max min typ max unit i sub v cc v cc = 2.5 v 5 20 ? (no bypass capacitor) v cc = 2.5 v 9 (47 ? bypass capacitor) v cc = 2.7 v 6 20 (no bypass capacitor) v cc = 2.7 v 11 (47 ? bypass capacitor) v cc = 5 v 13 16 (no bypass capacitor) v cc = 5 v 20 22 (47 ? bypass capacitor) i watch v cc v cc = 2.5 v 2.2 5 a (no bypass capacitor) v cc = 2.5 v 2.8 (47 ? bypass capacitor) v cc = 2.7 v 3.2 6 (no bypass capacitor) v cc = 2.7 v 3.8 (47 ? bypass capacitor) v cc = 5 v 6 10 (no bypass capacitor) v cc = 5 v 8 12 (47 ? bypass capacitor) pi stby v cc 5 10 a applicable pins power dissipation in subactive mode power dissipation in watch mode power dissipation in standby mode 254 appendix a cpu instruction set a.1 instruction notation operation notation rd8/16 general register (destination) (8 or 16 bits) rs8/16 general register (source) (8 or 16 bits) rn8/16 general register (8 or 16 bits) ccr condition code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #xx: 3/8/16 immediate data (3, 8, or 16 bits) d: 8/16 displacement (8 or 16 bits) @aa: 8/16 absolute address (8 or 16 bits) + addition subtraction multiplication division and logical or logical ? exclusive or logical ? move logical complement condition code notation symbol modified according to the instruction result * not fixed (value not guaranteed) 0 always cleared to 0 not affected by the instruction execution result 255 a.2 operation code map table a-1 is an operation code map. it shows the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. instruction when first bit of byte 2 (bit 7 of first instruction word) is 1. 256 table a-1 operation code map 5 = > 4 < = hi lo 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f nop bra mulxu bset shll shal sleep brn divxu bnot shlr shar stc bhi bclr rotxl rotl ldc bls btst rotxr rotr orc or bcc rts xorc xor bcs bsr bor bior bxor bixor band biand andc and bne rte ldc beq not neg bld bild bst bist add sub bvc bvs mov inc dec bpl jmp adds subs bmi eepmov mov cmp bge blt addx subx bgt jsr daa das ble mov add addx cmp subx or xor and mov mov * " # * + 3 the push and pop instructions are identical in machine language to mov instructions. note: * bit manipulation instruction 257 a.3 number of states required for execution table a-2 instruction set mnemonic operation i h n z v c mov.b #xx:8, rd b #xx:8 ? rd8 2 0? mov.b rs, rd b rs8 ? rd8 2 0? mov.b @rs, rd b @rs16 ? rd8 2 0? mov.b @(d:16, rs), rd b @(d:16, rs16) ? rd8 4 0? mov.b @rs+, rd b @rs16 ? rd8 2 0? rs16+1 ? rs16 mov.b @aa:8, rd b @aa:8 ? rd8 2 0? mov.b @aa:16, rd b @aa:16 ? rd8 4 0? mov.b rs, @rd b rs8 ? @rd16 2 0? mov.b rs, @(d:16, rd) b rs8 ? @(d:16, rd16) 4 0? mov.b rs, @?d b rd16? ? rd16 2 0? rs8 ? @rd16 mov.b rs, @aa:8 b rs8 ? @aa:8 2 0? mov.b rs, @aa:16 b rs8 ? @aa:16 4 0? mov.w #xx:16, rd w #xx:16 ? rd 4 0? mov.w rs, rd w rs16 ? rd16 2 0? mov.w @rs, rd w @rs16 ? rd16 2 0? mov.w @(d:16, rs), rd w @(d:16, rs16) ? rd16 4 0? mov.w @rs+, rd w @rs16 ? rd16 2 0? rs16+2 ? rs16 mov.w @aa:16, rd w @aa:16 ? rd16 4 0? mov.w rs, @rd w rs16 ? @rd16 2 0? mov.w rs, @(d:16, rd) w rs16 ? @(d:16, rd16) 4 0? mov.w rs, @?d w rd16? ? rd16 2 0? rs16 ? @rd16 mov.w rs, @aa:16 w rs16 ? @aa:16 4 0? pop rd w @sp ? rd16 2 0? sp+2 ? sp push rs w sp? ? sp 2 0? rs16 ? @sp #xx:8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa:8/16 @(d:8, pc) @@aa no. of states addressing mode/ instruction length (bytes) condition code operand size 258 table a-2 instruction set (cont) mnemonic operation i h n z v c eepmov if r4l 0 then 4 ? repeat @r5 ? @r6 r5+1 ? r5 r6+1 ? r6 r4l? ? r4l until r4l=0 else next add.b #xx:8, rd b rd8+#xx:8 ? rd8 2 2 add.b rs, rd b rd8+rs8 ? rd8 2 2 add.w rs, rd w rd16+rs16 ? rd16 2 2 addx.b #xx:8, rd b rd8+#xx:8 +c ? rd8 2 2 addx.b rs, rd b rd8+rs8 +c ? rd8 2 2 adds.w #1, rd w rd16+1 ? rd16 2 2 adds.w #2, rd w rd16+2 ? rd16 2 2 inc.b rd b rd8+1 ? rd8 2 ? daa.b rd b rd8 decimal adjust ? rd8 2 * * a 2 sub.b rs, rd b rd8?s8 ? rd8 2 2 sub.w rs, rd w rd16?s16 ? rd16 2 2 subx.b #xx:8, rd b rd8?xx:8? ? rd8 2 2 subx.b rs, rd b rd8?s8? ? rd8 2 2 subs.w #1, rd w rd16? ? rd16 2 2 subs.w #2, rd w rd16? ? rd16 2 2 dec.b rd b rd8? ? rd8 2 ? das.b rd b rd8 decimal adjust ? rd8 2 * * ? neg.b rd b 0?d ? rd 2 2 cmp.b #xx:8, rd b rd8?xx:8 2 2 cmp.b rs, rd b rd8?s8 2 2 cmp.w rs, rd w rd16?s16 2 2 #xx:8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa:8/16 @(d:8, pc) @@aa no. of states addressing mode/ instruction length (bytes) condition code operand size 259 table a-2 instruction set (cont) mnemonic operation i h n z v c mulxu.b rs, rd b rd8 rs8 ? rd16 2 14 divxu.b rs, rd b rd16 ? rs8 ? rd16 2 ?? 14 (rdh: remainder, rdl: quotient) and.b #xx:8, rd b rd8 #xx:8 ? rd8 2 0? and.b rs, rd b rd8 rs8 ? rd8 2 0? or.b #xx:8, rd b rd8 #xx:8 ? rd8 2 0? or.b rs, rd b rd8 rs8 ? rd8 2 0? xor.b #xx:8, rd b rd8 ? #xx:8 ? rd8 2 0? xor.b rs, rd b rd8 ? rs8 ? rd8 2 0? not.b rd b rd ? rd 2 0? shal.b rd b 2 2 shar.b rd b 2 0 2 shll.b rd b 2 0 2 shlr.b rd b 2 0 0 2 rotxl.b rd b 2 0 2 rotxr.b rd b 2 0 2 b 7 b 0 0 c c b 7 b 0 b 7 b 0 0 c b 7 b 0 0c c b 7 b 0 c b 7 b 0 #xx:8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa:8/16 @(d:8, pc) @@aa no. of states addressing mode/ instruction length (bytes) condition code operand size 260 table a-2 instruction set (cont) mnemonic operation i h n z v c rotl.b rd b 2 0 2 rotr.b rd b 2 0 2 bset #xx:3, rd b (#xx:3 of rd8) ? 1 2 2 bset #xx:3, @rd b (#xx:3 of @rd16) ? 1 4 8 bset #xx:3, @aa:8 b (#xx:3 of @aa:8) ? 1 4 8 bset rn, rd b (rn8 of rd8) ? 1 2 2 bset rn, @rd b (rn8 of @rd16) ? 1 4 8 bset rn, @aa:8 b (rn8 of @aa:8) ? 1 4 8 bclr #xx:3, rd b (#xx:3 of rd8) ? 0 2 2 bclr #xx:3, @rd b (#xx:3 of @rd16) ? 0 4 8 bclr #xx:3, @aa:8 b (#xx:3 of @aa:8) ? 0 4 8 bclr rn, rd b (rn8 of rd8) ? 0 2 2 bclr rn, @rd b (rn8 of @rd16) ? 0 4 8 bclr rn, @aa:8 b (rn8 of @aa:8) ? 0 4 8 bnot #xx:3, rd b (#xx:3 of rd8) ? 2 2 (#xx:3 of rd8) bnot #xx:3, @rd b (#xx:3 of @rd16) ? 4 8 (#xx:3 of @rd16) bnot #xx:3, @aa:8 b (#xx:3 of @aa:8) ? 4 8 (#xx:3 of @aa:8) bnot rn, rd b (rn8 of rd8) ? 2 2 (rn8 of rd8) bnot rn, @rd b (rn8 of @rd16) ? 4 8 (rn8 of @rd16) bnot rn, @aa:8 b (rn8 of @aa:8) ? 4 8 (rn8 of @aa:8) #xx:8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa:8/16 @(d:8, pc) @@aa no. of states addressing mode/ instruction length (bytes) condition code operand size c b 7 b 0 c b 7 b 0 261 table a-2 instruction set (cont) mnemonic operation i h n z v c btst #xx:3, rd b (#xx:3 of rd8) ? z 2 2 btst #xx:3, @rd b (#xx:3 of @rd16) ? z 4 6 btst #xx:3, @aa:8 b (#xx:3 of @aa:8) ? z 4 6 btst rn, rd b (rn8 of rd8) ? z 2 2 btst rn, @rd b (rn8 of @rd16) ? z 4 6 btst rn, @aa:8 b (rn8 of @aa:8) ? z 4 6 bld #xx:3, rd b (#xx:3 of rd8) ? c 2 2 bld #xx:3, @rd b (#xx:3 of @rd16) ? c 4 6 bld #xx:3, @aa:8 b (#xx:3 of @aa:8) ? c 4 6 bild #xx:3, rd b (#xx:3 of rd8) ? c 2 2 bild #xx:3, @rd b (#xx:3 of @rd16) ? c 4 6 bild #xx:3, @aa:8 b (#xx:3 of @aa:8) ? c 4 6 bst #xx:3, rd b c ? (#xx:3 of rd8) 2 2 bst #xx:3, @rd b c ? (#xx:3 of @rd16) 4 8 bst #xx:3, @aa:8 b c ? (#xx:3 of @aa:8) 4 8 bist #xx:3, rd b c ? (#xx:3 of rd8) 2 2 bist #xx:3, @rd b c ? (#xx:3 of @rd16) 4 8 bist #xx:3, @aa:8 b c ? (#xx:3 of @aa:8) 4 8 band #xx:3, rd b c (#xx:3 of rd8) ? c 2 2 band #xx:3, @rd b c (#xx:3 of @rd16) ? c 4 6 band #xx:3, @aa:8 b c (#xx:3 of @aa:8) ? c 4 6 biand #xx:3, rd b c (#xx:3 of rd8) ? c 2 2 biand #xx:3, @rd b c (#xx:3 of @rd16) ? c 4 6 biand #xx:3, @aa:8 b c (#xx:3 of @aa:8) ? c 4 6 bor #xx:3, rd b c (#xx:3 of rd8) ? c 2 2 bor #xx:3, @rd b c (#xx:3 of @rd16) ? c 4 6 bor #xx:3, @aa:8 b c (#xx:3 of @aa:8) ? c 4 6 bior #xx:3, rd b c (#xx:3 of rd8) ? c 2 2 bior #xx:3, @rd b c (#xx:3 of @rd16) ? c 4 6 #xx:8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa:8/16 @(d:8, pc) @@aa no. of states addressing mode/ instruction length (bytes) condition code operand size 262 table a-2 instruction set (cont) mnemonic operation i h n z v c bior #xx:3, @aa:8 b c (#xx:3 of @aa:8) ? c 4 6 bxor #xx:3, rd b c ? (#xx:3 of rd8) ? c 2 2 bxor #xx:3, @rd b c ? (#xx:3 of @rd16) ? c 4 6 bxor #xx:3, @aa:8 b c ? (#xx:3 of @aa:8) ? c 4 6 bixor #xx:3, rd b c ? (#xx:3 of rd8) ? c 2 2 bixor #xx:3, @rd b c ? (#xx:3 of @rd16) ? c 4 6 bixor #xx:3, @aa:8 b c ? (#xx:3 of @aa:8) ? c 4 6 bra d:8 (bt d:8) pc ? pc+d:8 2 4 brn d:8 (bf d:8) pc ? pc+2 2 4 bhi d:8 c z = 0 2 4 bls d:8 c z = 1 2 4 bcc d:8 (bhs d:8) c = 0 2 4 bcs d:8 (blo d:8) c = 1 2 4 bne d:8 z = 0 2 4 beq d:8 z = 1 2 4 bvc d:8 v = 0 2 4 bvs d:8 v = 1 2 4 bpl d:8 n = 0 2 4 bmi d:8 n = 1 2 4 bge d:8 n ? v = 0 2 4 blt d:8 n ? v = 1 2 4 bgt d:8 z (n ? v) = 0 2 4 ble d:8 z (n ? v) = 1 2 4 jmp @rn pc ? rn16 2 4 jmp @aa:16 pc ? aa:16 4 6 jmp @@aa:8 pc ? @aa:8 2 8 bsr d:8 sp? ? sp 2 6 pc ? @sp pc ? pc+d:8 #xx:8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa:8/16 @(d:8, pc) @@aa no. of states addressing mode/ instruction length (bytes) condition code operand size if condition is true then pc ? pc+d:8 else next; branching condition 263 table a-2 instruction set (cont) mnemonic operation i h n z v c jsr @rn sp? ? sp 2 6 pc ? @sp pc ? rn16 jsr @aa:16 sp? ? sp 4 8 pc ? @sp pc ? aa:16 jsr @@aa:8 sp? ? sp 2 8 pc ? @sp pc ? @aa:8 rts pc ? @sp 2 8 sp+2 ? sp rte ccr ? @sp 2 10 sp+2 ? sp pc ? @sp sp+2 ? sp sleep transit to sleep mode. 2 2 ldc #xx:8, ccr b #xx:8 ? ccr 2 2 ldc rs, ccr b rs8 ? ccr 2 2 stc ccr, rd b ccr ? rd8 2 2 andc #xx:8, ccr b ccr #xx:8 ? ccr 2 2 orc #xx:8, ccr b ccr #xx:8 ? ccr 2 2 xorc #xx:8, ccr b ccr ? #xx:8 ? ccr 2 2 nop pc ? pc+2 2 2 notes: set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0. if the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0. a set to 1 if decimal adjustment produces a carry; otherwise cleared to 0. ? the number of states required for execution is 4n+9 (n = value of r4l). ? set to 1 if the divisor is negative; otherwise cleared to 0. ? set to 1 if the divisor is zero; otherwise cleared to 0. #xx:8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa:8/16 @(d:8, pc) @@aa no. of states addressing mode/ instruction length (bytes) condition code operand size 264 appendix b on-chip registers b.1 on-chip registers (1) bit names bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 h'a0 star ?ta4sta3sta2sta1sta0 sci2 h'a1 edar ?da4eda3eda2eda1eda0 h'a2 scr2 i/o gap2 gap1 ps1 ps0 h'a3 stsr so2 ovr wt git stf last bit h'a4 not used to h'af h'b0 smr1 smr16 smr15 smr14 smr13 smr12 smr11 smr10 sci1 h'b1 sdru1 sdru17 sdru16 sdru15 sdru14 sdru13 sdru12 sdru11 sdru10 h'b2 sdrl1 sdrl17 sdrl16 sdrl15 sdrl14 sdrl13 sdrl12 sdrl11 sdrl10 h'b3 spr1 so1 last bit h'b4 h'b5 h'b6 h'b7 h'b8 h'b9 vfsr vflag kse sr4 sr3 sr2 sr1 sr0 h'ba vfdr flmo dm2 dm1 dm0 dr3 dr2 dr1 dr0 h'bb dbr vfde disp dbr3 dbr2 dbr1 dbr0 h'bc amr amr7 amr2 amr1 amr0 h'bd adrr adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 h'be adsr adsf h'bf notation: sci1: serial communication interface 1 sci2: serial communication interface 2 addr. (last register module byte) name name vfd con- troller/ driver a/d con- verter 265 b.1 on-chip registers (1) (cont) bit names bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 h'c0 tma tma3 tma2 tma1 tma0 timer a h'c1 tca tca7 tca6 tca5 tca4 tca3 tca2 tca1 tca0 h'c2 tmb tmb7 tmb2 tmb1 tmb0 timer b h'c3 tlb/tcb tlb7/ tlb6/ tlb5/ tlb4/ tlb3/ tlb2/ tlb1/ tlb0/ tcb7 tcb6 tcb5 tcb4 tcb3 tcb2 tcb1 tcb0 h'c4 tmc tmc7 tmc6 tmc5 tmc2 tmc1 tmc0 timer c h'c5 tlc/tcc tlc7/ tlc6/ tlc5/ tlc4/ tlc3/ tlc2/ tlc1/ tlc0/ tcc7 tcc6 tcc5 tcc4 tcc3 tcc2 tcc1 tcc0 h'c6 tmd clr edg timer d h'c7 tcd tcd7 tcd6 tcd5 tcd4 tcd3 tcd2 tcd1 tcd0 h'c8 tme tme7 tme2 tme1 tme0 timer e h'c9 tle/tce tle7/ tle6/ tle5/ tle4/ tle3/ tle2/ tle1/ tle0/ tce7 tce6 tce5 tce4 tce3 tce2 tce1 tce0 h'ca h'cb h'cc pwcr pwcr0 h'cd pwdru pwdru5 pwdru4 pwdru3 pwdru2 pwdru1 pwdru0 h'ce pwdrl pwdrl7 pwdrl6 pwdrl5 pwdrl4 pwdrl3 pwdrl2 pwdrl1 pwdrl0 h'cf h'd0 pdr0 pdr0 7 pdr0 6 pdr0 5 pdr0 4 pdr0 3 pdr0 2 pdr0 1 pdr0 0 h'd1 pdr1 pdr1 5 pdr1 4 pdr1 1 pdr1 0 h'd2 h'd3 h'd4 pdr4 pdr4 7 pdr4 6 pdr4 5 pdr4 4 pdr4 3 pdr4 2 pdr4 1 pdr4 0 h'd5 pdr5 pdr5 7 pdr5 6 pdr5 5 pdr5 4 pdr5 3 pdr5 2 pdr5 1 pdr5 0 h'd6 pdr6 pdr6 7 pdr6 6 pdr6 5 pdr6 4 pdr6 3 pdr6 2 pdr6 1 pdr6 0 h'd7 pdr7 pdr7 7 pdr7 6 pdr7 5 pdr7 4 pdr7 3 pdr7 2 pdr7 1 pdr7 0 h'd8 h'd9 pdr9 pdr9 7 pdr9 6 pdr9 5 pdr9 4 pdr9 3 pdr9 2 pdr9 1 pdr9 0 h'da h'db h'dc h'dd h'de h'df addr. (last register module byte) name name 14-bit pwm i/o ports 266 b.1 on-chip registers (1) (cont) bit names bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 h'e0 h'e1 pcr1 pcr1 5 pcr1 4 pcr1 1 pcr1 0 h'e2 h'e3 h'e4 h'e5 h'e6 h'e7 h'e8 h'e9 pcr9 pcr9 7 pcr9 6 pcr9 5 pcr9 4 pcr9 3 pcr9 2 pcr9 1 pcr9 0 h'ea h'eb pmr1 noise event irqc5 irqc4 irqc1 irqc0 cancel h'ec pmr2 up/ so2 si2 sck2 so1 si1 sck1 pwm down h'ed pmr3 so2 cs so1 pmos pmos h'ee pmr4 teo teo on freq vrfr h'ef pmr0 an7 an6 an5 an4 an3 an2 an1 an0 h'f0 syscr1 ssby sts2 sts1 sts0 lson h'f1 syscr2 dton h'f2 iegr ieg4 ieg1 ieg0 h'f3 ienr1 ien5 ien4 ien1 ien0 h'f4 ienr2 iendt iente ientd ientc ientb ienta h'f5 ienr3 ienad ienks iens2 iens1 h'f6 irr1 irri5 irri4 irri1 irri0 h'f7 irr2 irrdt irrte irrtd irrtc irrtb irrta h'f8 irr3 irrad irrks irrs2 irrs1 h'f9 h'fa h'fb h'fc h'fd h'fe h'ff addr. (last register module byte) name name system control i/o ports 267 b.2 on-chip registers (2) dbr?igit beginning register h'bb vfd controller register name address to which register is mapped name of on-chip peripheral module register acronym bit numbers initial bit values bit names and positions. dashes (? indicate reserved bits. read only write only read and write r w r/w possible types of access bit initial value read/write 7 vfde 0 r/w 6 disp 0 r/w 5 0 4 0 r/w 3 dbr3 0 r/w 0 dbr0 0 r/w 2 dbr2 0 r/w 1 dbr1 0 r/w 0 0 0 0 0 0 0 0 1 segment pin select fd to fd fd to fd , fs fd to fd , fs to fs fd to fd , fs to fs fd to fd , fs to fs fd to fd , fs to fs fd to fd , fs to fs fd to fd , fs to fs 0 1 2 3 4 5 6 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 7 7 7 7 7 7 7 7 *** fs to fs 7 7 7 7 7 7 7 7 6 5 4 3 2 1 0 don? care. * 0 display bit all segment pins are in non-illuminating state (pull-down state). digit pins continue operating. register and ram values are unchanged. display ram contents are output to segment pins. 1 full name of bit bit settings and descriptions note: 268 star?tart address register h'a0 sci2 edar?nd address register h'a1 sci2 scr2?erial control register h'a2 sci2 bit initial value read/write 7 1 6 1 5 1 4 sta4 0 r/w 3 sta3 0 r/w 0 sta0 0 r/w 2 sta2 0 r/w 1 sta1 0 r/w designates transfer starting address in range from h'ff80 to h'ff9f. bit initial value read/write 7 1 6 1 5 1 4 eda4 0 r/w 3 eda3 0 r/w 0 eda0 0 r/w 2 eda2 0 r/w 1 eda1 0 r/w designates transfer end address in range from h'ff80 to h'ff9f. bit initial value read/write 7 1 6 1 5 1 4 i/o 0 r/w 3 gap2 0 r/w 0 ps0 0 r/w 2 gap1 0 r/w 1 ps1 0 r/w 0 0 1 1 serial clock select /2, sck is output pin /4, sck is output pin /8, sck is output pin external clock, sck is input pin 0 1 0 1 f f f 2 2 2 2 0 0 1 1 gap select no gap insertion 1-clock gap insertion 2-clock gap insertion 8-clock gap insertion 0 1 0 1 0 1 transmit/receive select receive mode transmit mode 269 stsr?tatus register h'a3 sci2 bit initial value read/write 7 1 6 1 5 1 4 0 r/w 3 ovr not fixed r/w 0 stf 0 r/w 2 wt 0 r/w 1 git 0 r/w so2 last bit 0 1 extended data bit pin so output low pin so output high 2 2 0 start/busy flag [read] transfer stopped [write] transfer aborted [read] transfer in progress [write] starts transfer 1 0 1 gap interval flag insert gap every 16 bits insert gap every 8 bits 0 1 waiting flag [clear condition] when stsr is written 0 1 overrun flag [clear condition] when stsr is written [set condition] when overrun occurs [set condition] when 32-byte data buffer is read or written during transfer ** note: * cleared to 0 by a write access to stsr. 270 smr1?erial mode register 1 h'b0 sci1 sdru1?erial data register u1 h'b1 sci1 bit initial value read/write 7 1 6 smr16 0 w 5 smr15 0 w 4 smr14 0 w 3 smr13 0 w 0 smr10 0 w 2 smr12 0 w 1 smr11 0 w 0 1 operation mode select clock continuous output mode 8-bit transfer mode clock continuous output mode 16-bit transfer mode 0 not 00 0 0 not 00 0 0 1 clock select /1024, sck is output pin /256, sck is output pin /64, sck is output pin /32, sck is output pin /16, sck is output pin /8, sck is output pin /4, sck is output pin /2, sck is output pin not used not used not used not used not used not used not used external clock, sck is input pin f f f f f f f f 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 bit initial value read/write 7 sdru17 r/w 6 sdru16 r/w 5 sdru15 r/w 4 sdru14 r/w 3 sdru13 r/w 0 sdru10 r/w 2 sdru12 r/w 1 sdru11 r/w used to set transmit data and store received data. 8-bit transfer mode: not used 16-bit transfer mode: upper 8-bits of data register * *** ** ** note: * not fixed 271 sdrl1?erial data register l1 h'b2 sci1 spr1?erial port register 1 h'b3 sci1 bit initial value read/write 7 sdrl17 r/w 6 sdrl16 r/w 5 sdrl15 r/w 4 sdrl14 r/w 3 sdrl13 r/w 0 sdrl10 r/w 2 sdrl12 r/w 1 sdrl11 r/w used to set transmit data and store received data. 8-bit transfer mode: data register 16-bit transfer mode: lower 8-bits of data register * *** ** ** note: * not fixed bit initial value read/write 7 r/w 6 1 5 1 4 1 3 1 0 1 2 1 1 1 so1 last bit 0 0 extended data bit pin so output low pin so output high 1 1 * note: * not fixed 272 vfsr?fd segment control register h'b9 vfd controller/driver bit initial value read/write 7 vflag 0 r/w 6 kse 0 r/w 5 1 4 sr4 0 r/w 3 sr3 0 r/w 0 sr0 0 r/w 2 sr2 0 r/w 1 sr1 0 r/w 0 vfd/port switching flag all pins doubling as general-purpose ports and vfd pins are used as general-purpose ports. pins designated as digit or segment pins function as vfd pins. 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 segment pin select fs fs to fs fs to fs fs to fs fs to fs fs to fs fs to fs fs to fs fs to fs fs to fs fs to fs fs to fs fs to fs fs to fs fs to fs fs to fs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 fs to fs fs to fs fs to fs fs to fs fs to fs fs to fs fs to fs fs to fs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 16 17 18 19 20 21 22 23 0 1 key scan enable no key scan interval key scan interval added 273 vfdr?fd digit control register h'ba vfd controller/driver bit initial value read/write 7 flmo 0 r/w 6 dm2 0 r/w 5 dm1 0 r/w 4 dm0 0 r/w 3 dr3 0 r/w 0 dr0 0 r/w 2 dr2 0 r/w 1 dr1 0 r/w vfd mode bit 0 0 0 0 0 0 0 0 digit pin select fd to fd fd to fd fd to fd fd to fd fd to fd fd to fd fd to fd fd to fd 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 15 14 13 12 11 10 9 8 1 1 1 1 1 1 1 1 fd to fd fd to fd fd to fd fd to fd fd to fd fd to fd fd to fd fd 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 7 6 5 4 3 2 1 0 1 t = 1536/ , t = 96/ t = 768/ , t = 48/ digit dimmer ff digit dimmer ff 0 1 0 1 0 1 0 1 0 1 0 1 0 1 t digit t dimmer digit waveform select 274 dbr?igit beginning register h'bb vfd controller/driver bit initial value read/write 7 vfde 0 r/w 6 disp 0 r/w 5 1 4 0 r/w 3 dbr3 0 r/w 0 dbr0 0 r/w 2 dbr2 0 r/w 1 dbr1 0 r/w 0 0 0 0 0 0 0 0 1 digit/segment pin function select fd to fd fd to fd , fs fd to fd , fs to fs fd to fd , fs to fs fd to fd , fs to fs fd to fd , fs to fs fd to fd , fs to fs 0 1 2 3 4 5 6 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 7 7 7 7 7 7 7 7 *** fs to fs 7 7 7 7 7 7 7 7 6 5 4 3 2 1 0 don? care. * 0 display bit all segment pins are in non-illuminating state (pulled down). digit pins continue operating. register and ram values are unchanged. display ram contents are output to segment pins. 1 0 1 vfd enable vfd controller/driver is in reset state. vfd controller/driver is in active state. fd , fs to fs note: 275 amr?/d mode register h'bc a/d converter adrr?/d result register h'bd a/d converter bit initial value read/write 7 amr7 0 r/w 6 1 5 1 4 1 3 1 0 amr0 0 r/w 2 amr2 0 r/w 1 amr1 0 r/w 0 1 channel select analog input pin is an analog input pin is an analog input pin is an analog input pin is an analog input pin is an analog input pin is an analog input pin is an analog input pin is an 0 1 2 3 4 5 6 7 0 1 0 1 0 1 0 1 0 1 0 1 0 1 clock select conversion period is 62/ conversion period is 31/ f f bit initial value read/write 7 adr7 r 6 adr6 r 5 adr5 r 4 adr4 r 3 adr3 r 0 adr0 r 2 adr2 r 1 adr1 r a/d conversion result * *** ** ** note: * not fixed 276 adsr?/d start register h'be a/d converter tma?imer mode register a h'c0 timer a bit initial value read/write 7 adsf 0 r/w 6 1 5 1 4 1 3 1 0 1 2 1 1 1 0 a/d start flag [read] a/d conversion stopped or complete [write] a/d conversion aborted [read] a/d conversion in progress [write] starts a/d conversion 1 bit initial value read/write 7 1 6 1 5 1 4 1 3 tma3 0 r/w 0 tma0 0 r/w 2 tma2 0 r/w 1 tma1 0 r/w 0 1 clock select input source pss, /8192 input source pss, /4096 input source pss, /2048 input source pss, /512 input source pss, /256 input source pss, /128 input source pss, /32 input source pss, /8 input source psw, 2 s input source psw, 1 s input source psw, 0.5 s input source psw, 125 ms psw and tca reset f f f f f f f f 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 277 tca?imer counter a h'c1 timer a tmb?imer mode register b h'c2 timer b bit initial value read/write 7 tca7 0 r 6 tca6 0 r 5 tca5 0 r 4 tca4 0 r 3 tca3 0 r 0 tca0 0 r 2 tca2 0 r 1 tca1 0 r count value bit initial value read/write 7 tmb7 0 r/w 6 1 5 1 4 1 3 1 0 tmb0 0 r/w 2 tmb2 0 r/w 1 tmb1 0 r/w 0 1 clock select internal clock, /8192 internal clock, /2048 internal clock, /512 internal clock, /256 internal clock, /128 internal clock, /32 internal clock, /8 external clock, choice of rising or falling edge 0 1 0 1 0 1 0 1 0 1 0 1 0 1 auto reload function select free-running timer auto-reload timer f f f f f f f 278 tcb?imer counter b h'c3 timer b tlb?imer load register b h'c3 timer b bit initial value read/write 7 tcb7 0 r 6 tcb6 0 r 5 tcb5 0 r 4 tcb4 0 r 3 tcb3 0 r 0 tcb0 0 r 2 tcb2 0 r 1 tcb1 0 r count value bit initial value read/write 7 tlb7 0 w 6 tlb6 0 w 5 tlb5 0 w 4 tlb4 0 w 3 tlb3 0 w 0 tlb0 0 w 2 tlb2 0 w 1 tlb1 0 w reload value setting 279 tmc?imer mode register c h'c4 timer c tcc?imer counter c h'c5 timer c bit initial value read/write 7 tmc7 0 r/w 6 tmc6 0 r/w 5 tmc5 0 r/w 4 1 3 1 0 tmc0 0 r/w 2 tmc2 0 r/w 1 tmc1 0 r/w 0 1 clock select internal clock, /8192 internal clock, /2048 internal clock, /512 internal clock, /256 internal clock, /128 internal clock, /32 internal clock, /8 external clock, choice of rising or falling edge 0 1 0 1 0 1 0 1 0 1 0 1 0 1 count-up/down control up-counter down-counter hardware control via pin p9 /ud. high is down, low is up. f f f f f f f 0 1 * 7 0 1 auto-reload function select free-running timer auto-reload timer don? care. * note: bit initial value read/write 7 tcc7 0 r 6 tcc6 0 r 5 tcc5 0 r 4 tcc4 0 r 3 tcc3 0 r 0 tcc0 0 r 2 tcc2 0 r 1 tcc1 0 r count value 280 tlc?imer load register c h'c5 timer c tmd?imer mode register d h'c6 timer d tcd?imer counter d h'c7 timer d bit initial value read/write 7 tlc7 0 w 6 tlc6 0 w 5 tlc5 0 w 4 tlc4 0 w 3 tlc3 0 w 0 tlc0 0 w 2 tlc2 0 w 1 tlc1 0 w reload value setting bit initial value read/write 7 clr 0 w 6 1 5 1 4 1 3 1 0 edg 0 r/w 2 1 1 1 0 1 counter clear after this bit is set to 1 and tcd is initialized, it is automatically cleared by hardware. tcd is initialized to h'00. 0 1 edge select incremented at falling edge of event pin input incremented at rising edge of event pin input bit initial value read/write 7 tcd7 0 r 6 tcd6 0 r 5 tcd5 0 r 4 tcd4 0 r 3 tcd3 0 r 0 tcd0 0 r 2 tcd2 0 r 1 tcd1 0 r count value 281 tme?imer mode register e h'c8 timer e tce?imer counter e h'c9 timer e tle?imer load register e h'c9 timer e bit initial value read/write 7 tme7 0 r/w 6 1 5 1 4 1 3 1 0 tme0 0 r/w 2 tme2 0 r/w 1 tme1 0 r/w 0 1 clock select internal clock, /8192 internal clock, /4096 internal clock, /2048 internal clock, /512 internal clock, /256 internal clock, /128 internal clock, /32 internal clock, /8 0 1 0 1 0 1 0 1 0 1 0 1 0 1 auto-reload function select free-running timer auto-reload timer f f f f f f f f bit initial value read/write 7 tce7 0 r 6 tce6 0 r 5 tce5 0 r 4 tce4 0 r 3 tce3 0 r 0 tce0 0 r 2 tce2 0 r 1 tce1 0 r count value bit initial value read/write 7 tle7 0 w 6 tle6 0 w 5 tle5 0 w 4 tle4 0 w 3 tle3 0 w 0 tle0 0 w 2 tle2 0 w 1 tle1 0 w reload value setting 282 pwcr?wm control register h'cc 14-bit pwm pwdru?wm data register u h'cd 14-bit pwm pwdrl?wm data register l h'ce 14-bit pwm bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 pwcr0 0 w 2 1 1 1 0 clock select the input clock is /2. the conversion period is 16384/ , with a minimum modulation width of 1/ . 1 the input clock is /4. the conversion period is 32768/ , with a minimum modulation width of 2/ . f ff f ff bit initial value read/write 7 pwdrl7 0 w 6 pwdrl6 0 w 5 pwdrl5 0 w 4 pwdrl4 0 w 3 pwdrl3 0 w 0 pwdrl0 0 w 2 pwdrl2 0 w 1 pwdrl1 0 w lower 8 bits of data for pwm waveform generation bit initial value read/write 7 1 6 1 5 pwdru5 0 w 4 pwdru4 0 w 3 pwdru3 0 w 0 pwdru0 0 w 2 pwdru2 0 w 1 pwdru1 0 w upper 6 bits of data for pwm waveform generation 283 pdr0?ort data register 0 h'd0 i/o ports pdr1?ort data register 1 h'd1 i/o ports pdr4?ort data register 4 h'd4 i/o ports pdr5?ort data register 5 h'd5 i/o ports pdr6?ort data register 6 h'd6 i/o ports bit initial value read/write 7 pdr0 r 6 pdr0 r 5 pdr0 r 4 pdr0 r 3 pdr0 r 0 pdr0 r 2 pdr0 r 1 pdr0 r 7 65432 10 bit initial value read/write 7 6 5 pdr1 0 r/w 4 pdr1 0 r/w 3 1 0 pdr1 0 r/w 2 1 1 pdr1 0 r/w 54 0 ** 1 note: * pins p1 6 and p1 7 are input-only pins; whenever they are read, the pin level is read out. bit initial value read/write 7 pdr4 0 r/w 6 pdr4 0 r/w 5 pdr4 0 r/w 4 pdr4 0 r/w 3 pdr4 0 r/w 0 pdr4 0 r/w 2 pdr4 0 r/w 1 pdr4 0 r/w 3210 4 5 6 7 bit initial value read/write 7 pdr5 0 r/w 6 pdr5 0 r/w 5 pdr5 0 r/w 4 pdr5 0 r/w 3 pdr5 0 r/w 0 pdr5 0 r/w 2 pdr5 0 r/w 1 pdr5 0 r/w 3210 4 5 6 7 bit initial value read/write 7 pdr6 0 r/w 6 pdr6 0 r/w 5 pdr6 0 r/w 4 pdr6 0 r/w 3 pdr6 0 r/w 0 pdr6 0 r/w 2 pdr6 0 r/w 1 pdr6 0 r/w 3210 4 5 6 7 284 pdr7?ort data register 7 h'd7 i/o ports pdr9?ort data register 9 h'd9 i/o ports pcr1?ort control register 1 h'e1 i/o ports pcr9?ort control register 9 h'e9 i/o ports bit initial value read/write 7 pdr7 0 r/w 6 pdr7 0 r/w 5 pdr7 0 r/w 4 pdr7 0 r/w 3 pdr7 0 r/w 0 pdr7 0 r/w 2 pdr7 0 r/w 1 pdr7 0 r/w 3210 4 5 6 7 bit initial value read/write 7 pdr9 0 r/w 6 pdr9 0 r/w 5 pdr9 0 r/w 4 pdr9 0 r/w 3 pdr9 0 r/w 0 pdr9 0 r/w 2 pdr9 0 r/w 1 pdr9 0 r/w 3210 4 5 6 7 bit initial value read/write 7 1 6 1 5 pcr1 0 w 4 pcr1 0 w 3 1 0 pcr1 0 w 2 1 1 pcr1 0 w 54 10 0 1 port 1 i/o select input port output port bit initial value read/write 7 pcr9 0 w 6 pcr9 0 w 5 pcr9 0 w 4 pcr9 0 w 3 pcr9 0 w 0 pcr9 0 w 2 pcr9 0 w 1 pcr9 0 w 5432 10 6 7 0 1 port 9 i/o select input port output port 285 pmr1?ort mode register 1 h'eb i/o ports bit initial value read/write 6 event 0 r/w 5 irqc5 0 r/w 4 irqc4 0 r/w 3 1 0 irqc0 0 r/w 2 1 1 irqc1 0 r/w 0 1 p1 /irq pin function switch p1 pin function irq pin function 00 0 0 0 1 p1 /irq pin function switch p1 pin function irq pin function 11 1 1 0 1 p1 /irq pin function switch p1 pin function irq pin function 44 4 4 7 0 r/w noise cancel 0 1 p1 /irq /tmoe pin function switch p1 /tmoe pin function * irq pin function 55 5 5 0 1 p1 /event pin function switch p1 pin function event pin function 6 6 0 noise cancel irq pin noise cancel function off 0 1 irq pin noise cancel function on 0 note: * for the switching between p1 5 and tmoe pin functions see under pmr4. 286 pmr2?ort mode register 2 h'ec i/o ports bit initial value read/write 6 so2 0 r/w 5 si2 0 r/w 4 sck2 0 r/w 3 so1 0 r/w 0 pwm 0 r/w 2 si1 0 r/w 1 sck1 0 r/w 0 1 p9 /pwm pin function switch p9 pin function pwm pin function 0 0 0 1 p9 /sck pin function switch p9 pin function sck pin function 11 1 1 0 1 p9 /si pin function switch p9 pin function si pin function 21 2 1 0 1 p9 /so pin function switch p9 pin function so pin function 31 3 1 0 1 p9 /sck pin function switch p9 pin function sck pin function 42 4 2 7 0 r/w up/ down 0 1 p9 /si /cs pin function switch p9 pin function si /cs pin function * 51 5 1 0 1 p9 /so pin function switch p9 pin function so pin function 6 6 p9 /ud pin function switch 2 2 0 1 p9 pin function ud pin function 7 7 note: * for the switching between si 1 and cs pin functions see under pmr3. 287 pmr3?ort mode register 3 h'ed i/o ports bit initial value read/write 7 1 6 0 r/w 5 cs 0 r/w 4 1 3 0 r/w 0 1 2 1 1 1 so2 pmos so1 pmos 0 1 so pin pmos on/off so pin pmos buffer on. cmos output. so pin pmos off. nmos open-drain output. 1 1 1 pmr2 si2 chip select output select p9 pin function si pin function cs pin function 5 pmr3 cs p9 /si /cs pin function switch 52 2 0 1 0 1 0 1 0 1 so pin pmos on/off so pin pmos buffer on. cmos output. so pin pmos off. nmos open-drain output. 2 2 2 288 pmr4?ort mode register 4 h'ee i/o ports pmr0?ort mode register 0 h'ef i/o ports bit initial value read/write 7 teo 0 r/w 6 teo on 0 r/w 5 freq 0 r/w 4 vrfr 0 r/w 3 1 0 1 2 1 1 1 pmr1 irqc5 timer e output control p1 pin function tmoe pin function (off) tmoe pin function (on) tmoe pin function (on) tmoe pin function (on) 5 teo 0 0 0 0 0 0 1 1 1 1 pmr4 teo on 0 1 1 1 freq 0 1 vrfr 0 0 1 p1 /irq /tmoe pin function switch 5 5 standard i/o port low-level output fixed-frequency output: /2048 fixed-frequency output: /1024 pin status variable-frequency output: output toggles at each timer e overflow external interrupt input irq pin function 5 f f *** ** * ** ** 1 don? care. note: * bit initial value read/write 7 an7 0 w 6 an6 0 w 5 an5 0 w 4 an4 0 w 3 an3 0 w 0 an0 0 w 2 an2 0 w 1 an1 0 w 0 1 analog input select general-purpose input port analog input channel 289 syscr1?ystem control register 1 h'f0 system control syscr2?ystem control register 2 h'f1 system control bit initial value read/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 lson 0 r/w 0 0 2 0 r/w 1 0 0 0 0 0 1 standby timer select wait time = 8192 states wait time = 16384 states wait time = 32768 states wait time = 65536 states wait time = 131072 states 0 0 1 1 0 1 0 1 0 1 low-speed on flag cpu runs on system clock ( ) cpu runs on subclock ( ) * 2 f f sub 0 1 standby sleep mode entered after sleep instruction is executed. standby mode entered after sleep instruction is executed. * 1 * 3 * 3 notes: 1. write is enabled in active mode only. 2. this relates to the transitions between operation modes, so functioning depends on the combination of this bit with other control bits and interrupts. for details see 3.3, system modes. 3. don? care. bit initial value read/write 7 1 6 1 5 1 4 1 3 dton 0 w * 0 0 r/w 2 1 1 0 r/w 0 direct transfer on flag in subactive mode, watch mode is entered when a sleep instruction is executed. 1 in subactive mode, if lson bit = 0, active mode is entered via watch mode when a sleep instruction is executed. note: * write is enabled in subactive mode only. 290 iegr?rq edge select register h'f2 system control ienr1?nterrupt enable register 1 h'f3 system control bit initial value read/write 7 1 6 1 5 1 4 ieg4 0 r/w 3 1 0 ieg0 0 r/w 2 1 1 ieg1 0 r/w 0 1 irq input edge select rising edge detected. falling edge detected. 4 0 1 irq input edge select rising edge detected. falling edge detected. 0 0 1 irq input edge select rising edge detected. falling edge detected. 1 bit initial value read/write 7 1 6 1 5 ien5 0 r/w 4 ien4 0 r/w 3 0 r/w 0 ien0 0 r/w 2 0 r/w 1 ien1 0 r/w 0 1 irq interrupt enable interrupts disabled. interrupts enabled. 5 0 1 irq interrupt enable interrupts disabled. interrupts enabled. 4 0 1 irq interrupt enable interrupts disabled. interrupts enabled. 1 0 1 irq interrupt enable interrupts disabled. interrupts enabled. 0 291 ienr2?nterrupt enable register 2 h'f4 system control ienr3?nterrupt enable register 3 h'f5 system control bit initial value read/write 7 0 r/w 6 0 r/w 5 iendt 0 r/w 4 iente 0 r/w 3 ientd 0 r/w 0 ienta 0 r/w 2 ientc 0 r/w 1 ientb 0 r/w 0 1 dton interrupt enable interrupts disabled. interrupts enabled. 0 1 timer e interrupt enable interrupts disabled. interrupts enabled. 0 1 timer d interrupt enable interrupts disabled. interrupts enabled. 0 1 timer c interrupt enable interrupts disabled. interrupts enabled. 0 1 timer b interrupt enable interrupts disabled. interrupts enabled. 0 1 timer a interrupt enable interrupts disabled. interrupts enabled. bit initial value read/write 7 ienad 0 r/w 6 ienks 0 r/w 5 1 4 1 3 1 0 iens1 0 r/w 2 1 1 iens2 0 r/w 0 1 sci1 interrupt enable interrupts disabled. interrupts enabled. 0 1 sci2 interrupt enable interrupts disabled. interrupts enabled. 0 1 key scan interrupt enable interrupts disabled. interrupts enabled. 0 1 a/d conversion complete interrupt enable interrupts disabled. interrupts enabled. 292 irr1?nterrupt request register 1 h'f6 system control bit initial value read/write 7 1 6 1 5 irri5 0 r/w * 4 irri4 0 r/w * 3 0 0 irri0 0 r/w * 2 0 1 irri1 0 r/w * 0 1 irq interrupt request no interrupt request interrupt request raised 5 0 1 irq interrupt request no interrupt request interrupt request raised 4 0 1 irq interrupt request no interrupt request interrupt request raised 1 0 1 irq interrupt request no interrupt request interrupt request raised 0 note: * only 0 can be written, to clear the flag. 293 irr2?nterrupt request register 2 h'f7 system control irr3?nterrupt request register 3 h'f8 system control bit initial value read/write 7 0 6 0 5 irrdt 0 r/w * 4 irrte 0 r/w * 3 irrtd 0 r/w * 0 irrta 0 r/w * 2 irrtc 0 r/w * 1 irrtb 0 r/w * 0 1 dton interrupt request no interrupt request interrupt request 0 1 timer e interrupt request no interrupt request interrupt request 0 1 timer d interrupt request no interrupt request interrupt request 0 1 timer c interrupt request no interrupt request interrupt request 0 1 timer b interrupt request no interrupt request interrupt request 0 1 timer a interrupt request no interrupt request interrupt request note: * only 0 can be written, to clear the flag. bit initial value read/write 7 irrad 0 r/w * 6 irrks 0 r/w * 5 1 4 1 3 1 0 irrs1 0 r/w * 2 1 1 irrs2 0 r/w * 0 1 sci1 interrupt request no interrupt request interrupt request 0 1 sci2 interrupt request no interrupt request interrupt request 0 1 key scan interrupt request no interrupt request interrupt request 0 1 a/d conversion complete interrupt request no interrupt request interrupt request note: * only 0 can be written, to clear the flag. 294 appendix c i/o port block diagrams c.1 port 0 block diagram figure c-1 port 0 block diagram p0 n v sel internal data bus pmr0 (bit n) pmr0: port mode register 0 n = 0 to 7 in a/d converter 295 c.2 port 1 block diagram figure c-2 (a) port 1 block diagram (pins p1 0 , p1 1 , and p1 4 ) p1 n v cc option v cc v ss stby irq internal data bus pdr1 (bit n) pmr1 (bit n) pdr1: port data register 1 pmr1: port mode register 1 pcr1: port control register 1 n = 0, 1, 4 p1 : irq p1 : irq p1 : irq 0 1 4 0 1 4 pcr1 (bit n) 296 figure c-2 (b) port 1 block diagram (pin p1 5 ) p1 5 v cc option v cc v ss stby timer e tmoe teo irq 5 internal data bus pdr1 (bit 5) pmr1 (bit 5) pcr1 (bit 5) pdr1: port data register 1 pmr1: port mode register 1 pcr1: port control register 1 teo: port mode register 4, bit 7 tmoe: square wave output 297 figure c-2 (c) port 1 block diagram (pin p1 6 ) figure c-2 (d) port 1 block diagram (pin p1 7 ) p1 6 option stby event internal data bus pdr1 (bit 6) pmr1: port mode register 1 edg (edge select) timer d p1 7 v disp option internal data bus v ss 298 c.3 port 4 block diagram figure c-3 port 4 block diagram p4 n option v cc stby vfd controller/ driver internal data bus decoder sgdl pdr4 (bit n) pdr4: port data register 4 sgdl: segment data latch ltclk: segment data latch clock sr to sr : vfd segment control register bits 4 to 0 vflag: vfd segment control register bit 7 n = 0 to 7 sr to sr vflag ltclk ram data v disp 40 40 299 c.4 port 5 block diagram figure c-4 port 5 block diagram p5 n option v cc stby vfd controller/ driver internal data bus decoder sgdl pdr5 (bit n) pdr5: port data register 5 sgdl: segment data latch ltclk: segment data latch clock sr to sr : vfd segment control register bits 4 to 0 vflag: vfd segment control register bit 7 n = 0 to 7 sr to sr vflag ltclk ram data v disp 40 40 300 c.5 port 6 block diagram figure c-5 port 6 block diagram fd p6 n option v cc stby vfd controller/ driver internal data bus pdr6 (bit n) pdr6: port data register 6 sgdl: segment data latch ltclk: segment data latch clock fd: digit output waveform ram data v disp decoder sgdl dbr3 to dbr0 dr3 to dr0 sr4 to sr0 vflag ltclk dbr3 to dbr0: digit beginning register bits 3 to 0 dr3 to dr0: vfd digit control register bits 3 to 0 sr4 to sr0: vfd segment control register bits 4 to 0 vflag: vfd segment control register bit 7 n = 0 to 7 301 c.6 port 7 block diagram figure c-6 port 7 block diagram p7 n option v cc stby vfd controller/ driver internal data bus decoder pdr7 (bit n) pdr7: port data register 7 fd: digit output waveform dr3 to dr0: vfd digit control register bits 3 to 0 vflag: vfd segment control register bit 7 n = 0 to 7 fd dr3 to dr0 v disp vflag 302 c.7 port 9 block diagram figure c-7 (a) port 9 block diagram (pin p9 0 ) p9 0 v cc option v cc v ss stby pwm pmr2 (bit 0) pdr9: port data register 9 pmr2: port mode register 2 pcr9: port control register 9 pdr9 (bit 0) pcr9 (bit 0) internal data bus pwm 303 figure c-7 (b) port 9 block diagram (pins p9 1 and p9 4 ) p9 n v cc option v cc v ss stby sci pmr2 (bit n) pdr9: port data register 9 pmr2: port mode register 2 pcr9: port control register 9 n = 1 and 4 pdr9 (bit n) pcr9 (bit n) internal data bus exck scko scki 304 figure c-7 (c) port 9 block diagram (pin p9 2 ) p9 2 v cc option v cc v ss stby si internal data bus pdr9 (bit 2) pmr2 (bit 2) pdr9: port data register 9 pmr2: port mode register 2 pcr9: port control register 9 sci pcr9 (bit 2) 305 figure c-7 (d) port 9 block diagram (pins p9 3 and p9 6 ) p9 n v cc option v cc v ss stby sci pmr2 (bit n) pdr9: port data register 9 pmr2: port mode register 2 pcr9: port control register 9 n = 3 and 6 pdr9 (bit n) pcr9 (bit n) internal data bus so pmr3 p9 : bit 3 p9 : bit 6 3 6 306 figure c-7 (e) port 9 block diagram (pin p9 5 ) p9 5 v cc option v cc v ss stby sci pmr2 (bit 5) pdr9: port data register 9 pmr2: port mode register 2 pcr9: port control register 9 pdr9 (bit 5) pcr9 (bit 5) internal data bus cs si pmr3 (bit 5) 307 figure c-7 (f) port 9 block diagram (pin p9 7 ) p9 7 v cc option v cc v ss stby ud internal data bus pdr9 (bit 7) pmr2 (bit 7) pdr9: port data register 9 pmr2: port mode register 2 pcr9: port control register 9 timer c pcr9 (bit 7) 308 appendix d port states in each processing state table d-1 port states mode port pins reset sleep standby watch subactive active p0 7 to p0 0 hi-z hi-z hi-z hi-z hi-z standard input port p1 7 hi-z hi-z hi-z hi-z hi-z high-voltage input port p1 6 hi-z or pulled up hi-z or hi-z hi-z hi-z standard pulled up input port p1 5 , p1 4 , hi-z or pulled up prev. state hi-z hi-z hi-z standard i/o p1 1 , p1 0 port p4 7 to p4 0 hi-z or prev. state hi-z or hi-z or hi-z or high-voltage pulled down pulled down pulled down pulled down i/o port p5 7 to p5 0 hi-z or prev. state hi-z or hi-z or hi-z or high-voltage pulled down pulled down pulled down pulled down i/o port p6 7 to p6 0 hi-z or prev. state hi-z or hi-z or hi-z or high-voltage pulled down pulled down pulled down pulled down i/o port p7 7 to p7 0 hi-z or prev. state hi-z or hi-z or hi-z or high-voltage pulled down pulled down pulled down pulled down i/o port p9 7 to p9 0 hi-z or pulled up prev. state hi-z hi-z hi-z standard i/o port notation: hi-z: high-impedance state prev. state: input pins are in high-impedance state. output pins hold their previous output. hi-z or pulled up: standard ports for which the pull-up mos mask option is chosen are pulled up; ports without the pull-up mos option are in the high-impedance state. hi-z or pulled down: high-voltage ports for which the pull-down mos mask option is chosen are pulled down; ports without the pull-down mos option are in the high- impedance state. 309 notes: 1. when mos pull-up is chosen as a mask option with standard ports, the pull-ups are always on in active mode and sleep mode, regardless of the port control register (pcr) and port data register (pdr) settings. the pull-ups are off in power-down modes other than sleep mode. 2. the input gates of pins selected for peripheral function input remain on even in power- down modes. their input levels must be held fixed in order to avoid increased power dissipation. 3. the states indicated above for p1 7 apply when this pin is designated as a high-voltage input pin by mask option. 310 appendix e list of mask options hd6433712, hd6433713 and hd6433714 311 notes: 1. 2. the wide temperature range specification and i specification are special specifications. there is no j specification for these products. please contact your local hitachi representative for details. rom data submitted in an eprom must be written starting from address h'0000 in accordance with the memory map of the particular microcontroller. for data outside the rom area on the memory map use h'ff. fp-64a dp-64s (3) package if e (mos pull-down) is selected as an option for one or more high-voltage pins, v disp must be selected for the p1 7 /v disp pin. note: p1 7 : no mos pull-down (d) v disp (2) p1 7 /v disp crystal oscillator ceramic oscillator external clock (4) oscillator at osc 1 and osc 2 used not used (5) oscillator at x 1 and x 2 f osc = f osc = f osc = f x x 1 mhz mhz mhz = 32.768 khz = v cc c: no mos pull-up e: with mos pull-down date of order company address name rom code name part no. , 19 b: with mos pull-up d: no mos pull-down (1) i/o options pin i/o i/o option b c de p1 0 /irq 0 p1 1 /irq 1 p1 4 /irq 4 p1 5 /irq 5 /tmoe p1 6 /event p4 0 /fs 16 p4 1 /fs 17 p4 2 /fs 18 p4 3 /fs 19 p4 4 /fs 20 p4 5 /fs 21 p4 6 /fs 22 p4 7 /fs 23 p1 7 /v disp p9 0 /pwm p9 1 /sck 1 p9 2 /si 1 p9 3 /so 1 p9 4 /sck 2 p9 5 /si 2 /cs p9 6 /so 2 p9 7 /ud pin i/o i/o option bcde p6 0 /fd 0 /fs 7 p6 1 /fd 1 /fs 6 p6 2 /fd 2 /fs 5 p6 3 /fd 3 /fs 4 p6 4 /fd 4 /fs 3 p6 5 /fd 5 /fs 2 p6 6 /fd 6 /fs 1 p6 7 /fd 7 /fs 0 p7 0 /fd 8 p7 1 /fd 9 p7 2 /fd 10 p7 3 /fd 11 p7 4 /fd 12 p7 5 /fd 13 p7 6 /fd 14 i/o i/o i/o i/o i i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o standard pins high-voltage pins fill in (2) below high-voltage pins please indicate the selected specifications by marking the appropriate box (with an or ? mark). the shaded boxes cannot be selected. p5 0 /fs 15 p5 1 /fs 14 p5 2 /fs 13 p5 3 /fs 12 p5 4 /fs 11 p5 5 /fs 10 p5 6 /fs 9 p5 7 /fs 8 standard pins p7 7 /fd 15 hd6433712 hd6433713 hd6433714 appendix f rise time and fall time of high-voltage pins with the mask rom versions there is a choice of high-voltage pin output configurations. either pmos open-drain (d) or mos pull-down (e) may be selected. (only pmos open-drain is available as the output configuration of high-voltage pins on ztat versions.) the rise time t r and fall time t f of high-voltage pin output are as follows. it is possible to estimate t r and t f from the time constant t = c . r (time up to 63% of rise or fall). t r : the time constant is determined by the pmos on-resistance and load capacitance. the dc on-resistance is approximately 200 (based on v oh = v cc ?3 v at ? oh = 15 ma, 3/0.015 = 200). the ac on-resistance however, includes the non-saturation state when the pmos transistor turns on (it is not a constant-current source), resulting in a longer time constant. assuming a load capacitance of 30 pf at high-voltage pins, the minimum value is approximately 20 ns. t f : the time constant is determined by the pull-down resistance and load capacitance (including wiring capacitance, etc.). as an example, assuming a pull-down resistance of 5 k and load capacitance of 30 pf, the following is derived. t f 3 5 10 3 30 10 ?2 = 150 10 ? (150 ns) mos pull-down resistance varies from 45 k to 300 k , so all due care must be taken in timing design. note: if pull-down resistance is made too small in an attempt to speed up the fall time, ? oh will increase, limiting the output high-level voltage (v oh ). pull-down resistance must be set to a suitable value taking into consideration both operation speed and the output high level. 63% 63% t f t r v or v ss disp v cc h8/3714 series microcontroller pull-down resistance load capacitance 312 appendix g package dimensions figures g-1 and g-2 show the external dimensions of the fp-64a and dp-64s packages, respectively, for the h8/3712, h8/3713 and h8/3714. unit: mm figure g-1 external dimensions (fp-64a) unit: mm figure g-2 external dimensions (dp-64s) 313 |
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